In the semiconductor industry, field returns have a negative impact with large costs and potential loss of reputation. As a consequence, a good coverage of the production tests with respect to the common manufacturing defects is essential to ensure the quality of the product to be delivered. Defect simulation is imperative to obtain coverage, however long simulation duration of the production tests can be a huge obstacle. Hence, there is an emergent need for novel methodologies to obtain coverage analysis of AMS chip production tests. In this paper, we address several aspects that are necessary to develop such a methodology. We first propose a method to identify a fault model that mimics the common manufacturing defects and extract all such faults from the DUT layout, we then develop a test ordering procedure that for a given fault selects the test from an existing test suite that is the most likely to detect the fault. The test ordering technique allows to avoid the execution of many tests during the coverage analysis and thus save considerable amounts of simulation time. We demonstrate the applicability and efficiency of the resulting techniques on an AMS design from Infineon Technologies AG.
In Proc. of ITC'18, the International Test Conference, Phoenix, Arizona, USA, October, 2018, IEEE.
*This work was partially supported by the NSF-Frontiers Cyber-Cardia
Award, the US-AFOSR Arrive Award, the EU-Artemis EMC2 Award, the
EU-Ecsel Semi40 Award, the EU-Ecsel Productive 4.0 Award, the
AT-FWF-NFN RiSE Award, the AT-FWF-LogicCS-DC Award, the AT-FFG
Harmonia Award, the AT-FFG Em2Apps Award, and the TUW-CPPS-DK Award.