PhD on Mixed Signal IC Verification

The goal of this PhD activity is to develop and investigate new methods and concepts for verification of Mixed-Signal Smart Power ICs for various automotive applications, like lighting, heating, power distribution, motor driving etc. Short time to market requirements, increasing complexity, miniaturisation of modern ICs and latest safety standards result in stringent requirements and considerable effort for the pre-silicon verification process. To satisfy these needs Infineon Technologies Austria together with KAI and the Vienna University of Technology will set up a research project on new methods and concepts for IC verification.

Within this PhD activity your tasks will be:

  • Behavioral modelling of analog macro-blocks in VHDL, VHDL-AMS, Verilog-A(MS)
  • Definition of analog mixed-signal test metrics including coverage models and fault models
  • Evaluation of the performances of “concolic” (concrete and symbolic) test methods on smart power ICs
  • Generation of automatic test patterns for full chip pre and post verification to meet the targeted coverage goals
  • Investigation on SAT and SMT methods for ATPG (Automatic Test Pattern Generation)


The duration of the PhD-project is 3 years. The student will be placed at TU Vienna and will closely cooperate with the IC developments groups at Infineon Technologies and KAI in Villach. This project will be supervised by Prof. Radu Grosu (radu.grosu@tuwien.ac.at) from the Vienna University of Technology.

Your Profile

Must have an university degree in either electrical engineering with focus on digital design or in computer engineering with focus on embedded systems. Experience with modern EDA tools for the design of silicon devices is mandatory, as well as fluent English. Willingness to travel between Vienna and Villach, is required. Some industry experience and basic German skills are preferred.

Start Date

1. December 2014

Application

Applications can be submitted at https://recruitingapp-2721.de.umantis.com/Vacancies/5066/Description/2.