Practicals & Theses

List of practicals and theses at the institute (see also TI Research Presentations)

Java bytecode optimizer

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Martin SCHÖBERL, 13. 03. 2006

The standard Java compiler (javac) performs no optimization at all. Optimization is postboned to the JIT compiler. For a Java processor (or an interpreting JVM) this is not an optimal solution. The idea is to implement standard compiler optimizations and processor specific optimizations at the bytecode level. See: JVM Specification, Byte Code Engineering Library and ASM


TTNoC boundary test with interleaved messages (New, exciting, and promising!)

CPS: Dipl.-Ing. Harald PAULITSCH, 12. 02. 2009

Masterarbeit ::: Seminar mit Bachelorarbeit + Projektpraktikum ::: Building on the Unique Selling Proposition of time-triggered systems, the predictability, interleave test messages with regular traffic to iteratively identify and ultimately pinpoint faulty network links.


Aufbau eines CAN Systems (Lötpraktikum)

CPS: Projektass. Dipl.-Ing. Dr.techn. Armin WASICEK, 22. 02. 2011

Ziel des Praktikums ist es ein CAN System mit AVR Mikrocontrollern aufzubauen.


Camera Integration in Windows Embedded

CPS: Projektass. Dipl.-Ing. Dr.techn. Armin WASICEK, 04. 04. 2012

The goal of the Master's thesis is to develop a software to integrate video streams from three different cameras in Windows Embedded Compact 7. A special application (which is already available for Desktop Windows) will run several image processing algorithms on the captured video streams. This existing application uses DirectShow which is not available under Windows Embedded. Therefore a similar functionality has to be implemented.

The thesis will be carried out as an "Industrie-Diplomarbeit" together with an industrial company. A funding will be provided by the company.


Can we trust the chips of the future?

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 07. 08. 2012

Recently concerns have been raised that some chips used in military applications have security problems: The suspect is that the fab has introduced a backdoor into the hardware. Announcements like this raise the question whether hardware is becoming prone to security threads like trojans, backdoors etc. that have so far been deemed to be "software only". Your task will be to investigate this issue in a literature study and develop a catalog of potential threads and related case reports.


Implementation Styles for Asynchronous Data Pipelines

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Bakk.techn. Robert NAJVIRT, 19. 10. 2012

Asynchronous Pipelines are typically controlled by a so-called Muller-Pipeline that handles the flow control in an elastic way. The control singnals created by the Muller-Pipeline are then connected to storage elements (registers) in order to manage the data flow appropriately. There are, however, many ways of doing this; like using both clock edges or just one, using flip flops or latches, by 4-phase or 2-phase protocol etc.
Your task will be to review the state of the art in this field, encompassing both bundled-data as well as quasi-delay insensitive pipelines. The result will be a comprehensive compilation of the methods, with each method being associated with the related pros and cons, preferred application cases as well as references and use cases from the literature. In the practical part of this work you will implement the methods and compare their performance, area overheads energy consumption etc.


Evaluation of operating systems for microcontrollers in wireless embedded systems

ECS: Projektass.(FWF) Dipl.-Ing. BSc Martin PERNER, 30. 01. 2014

The scope of this work is to evaluate the difference between operating systems, e.g., TinyOS and contiki, on battery powered AT86RF230 RCB motes, with regards to performance, code size and architectural design style.