Practicals & Theses

List of practicals and theses at the institute (see also TI Research Presentations)

Development of a Timing Analysis Tool for a specific Hardware Platform

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006

The task is to develop a timing analysis tool that allows to calculate the maximum execution time of real-time programs. The part of the tool to calculate the execution time already exists. What has to be done is to add a front end that can read assembly code or object code and construct and to build a timing model for a specific processor (Motorola MC68k or PPC, ARM, ...)

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Concepts of Execution Time Analysis studied on the Linux Kernel

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006

By using the source code of the Linux kernel one should analyse, what constructs or mechanisms could influence the timing behavior of the operating system. Optionally, the analysis could be done using Real-Time Linux as a case study.

The analysis should cover synchronisation mechanisms as well as scheduling techniques.

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Formal Specification of Real-Time Systems

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006

Within the project TeDES we have a research cooperation with industrial partners from the automotive industry to develop a test environment to systematically verify distributed safety-critical real-time systems.

Within this Masther's thesis one will work on model-based testing, with the focus on formal mechanisms for specifying real-time systems. Formal means, that the description has a well-defined meaning.

The aim of this work is to remove or reduce the error-prone and tedios process of generating test cases manually. This work is also of high practical significance in industry.

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Limitations on the Analyzability of Real-Time Systems

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006

To operate real-time sytems in a safe way, it is required to know the maximum execution time of the program code. However, there are problems to reason about the program behavior in general (c.f., the Halting Problem).


It is the goal of this work to analyze the problem from the other side, i.e., by analyzing what code structures are predictable. For this one has to also look on program analysis methods to reason about what properties can be derived by such an analysis. It is the goal of this work to find restrictions on the program structures, such that the execution time analysis becomes feasible.

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Safety-Requirements to Validate Real-Time Systems

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006

Within the project TeDES we have a research cooperation with industrial partners from the automotive industry to develop a test environment to systematically verify distributed safety-critical real-time systems.

Within this Masther's thesis one should study existing safety requirements on their impact on the systematic testing of real-time systems. The goal is to obtain a framework to specify test scenarious for the systematic test of distributed real-time systems.

The aim of this work is to remove or reduce the error-prone and tedios process of generating test cases manually. This work is also of high practical significance in industry.

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Predictable Cache Memory

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 10. 03. 2006

Cache memories are used to boost the performance of computer memory systems. While the performance benefit of caches is indeed substantial, the use of caches makes the calculation of the run times of code very difficult. The goal of this work is therefore to conceive a new type of hierarchical memory system, that allows for both, a high performance of program execution and a good predictability of code timing.

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WCET Analysis of Java Applications

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Martin SCHÖBERL, 13. 03. 2006

Worst-case execution time (WCET) estimates are essential for real-time systems. The theory for static WCET analysis is mature. However, the tools are still missing. The tool shall provide WCET estimates for Java real-time applications running on a Java processor (JOP) that is designed to be an easy target for WCET analysis.

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Implementation of a Measurement Framework for WCET Analysis Tools

CPS: Sven BÜNTE, 24. 04. 2008

Several processor types are used in the embedded domain, each of them demanding specific strategies to perform temporal measurements. The goal is to conveniently implement extensions of a framework that unifies some of these strategies. Strong programming skills in C++ are a requisite. Knowledge of MS Visual Studio and software engineering in general is beneficial.

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Design of a Repository for Embedded Real Time Applications

CPS: Sven BÜNTE, 10. 11. 2008

The FORmal Timing Analysis Suite is a framework for the validation of temporal requirements in the context of embedded real time systems. In cooperation with TU Darmstadt and partners from industry we are currently developing a tool that automatically provides timing properties for software and system architects.

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TTNoC boundary test with interleaved messages (New, exciting, and promising!)

CPS: Dipl.-Ing. Harald PAULITSCH, 12. 02. 2009

Masterarbeit ::: Seminar mit Bachelorarbeit + Projektpraktikum ::: Building on the Unique Selling Proposition of time-triggered systems, the predictability, interleave test messages with regular traffic to iteratively identify and ultimately pinpoint faulty network links.

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Visualization of Process Synchronization

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 30. 03. 2009

The goal of this project is to develop simulation software to illustrate the synchronization of processes via semaphores and illustrate deadlock behaviour.

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Autonomous-Car Simulator

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 31. 03. 2009

Within this project students develop a simulator for an autonomous model car that has to follow a given course.

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Worst-Case Execution-Time Analysis Tool for ARM Processor

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 31. 03. 2009

In this project students develop a worst-case execution-time analysis tool for an ARM7 micro controller board.

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Compilation for Predictable Real-Time Systems

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 01. 03. 2010

Usually, the focus of compiler writers is to generate fast code. Contrasting this, the goal of this thesis is to work on code generation strategies that produce code with predictable timing, i.e., the stability of the timing and a simple prediction of the worst-case execution time are in the center of interest.

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Algorithms with Stable Timing

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 31. 03. 2009

The goal of this thesis project is to develop new algorithms characterized by stable timing for a number of programming problems.

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Camera Integration in Windows Embedded

CPS: Projektass. Dipl.-Ing. Dr.techn. Armin WASICEK, 04. 04. 2012

The goal of the Master's thesis is to develop a software to integrate video streams from three different cameras in Windows Embedded Compact 7. A special application (which is already available for Desktop Windows) will run several image processing algorithms on the captured video streams. This existing application uses DirectShow which is not available under Windows Embedded. Therefore a similar functionality has to be implemented.

The thesis will be carried out as an "Industrie-Diplomarbeit" together with an industrial company. A funding will be provided by the company.

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Effects of Stuck-at Faults on Delay-Insensitive Logic

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Bakk.techn. Robert NAJVIRT, 07. 08. 2012

In contrast to the state-based principle of synchronous logic, the operation of Delay Insensitive (DI) asynchronous logic is characterized by transitions. Therefore DI logic will generally stop operation in case of a stuck-at fault. In most cases this will lead to a "fail-stop" behavior, and the circuit may correctly continue its operation without the need for state recovery once the fault has been removed. Your task will be to identify all cases where this may not be true, i.e. the circuit will encounter one or more erroneous transitions before the deadlock, so that its state is currupted and need recovery. For the analysis theoretic consideration shall be combined with simulations, and finally some selected examples shall be demonstrated on an FPGA implementation.

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Fault Masking in Synchronous and in Asynchronous Logic -- A Comparison

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Bakk.techn. Robert NAJVIRT, 07. 08. 2012

A fault is said to be masked if it affects a circuit but never creates an erroneous state and hence stays ineffective. In synchronous logic it is agreed that faults can be masked on three levels, namely (1) electrical, (2) logical and (3) temporal level. While it can be expected that (1) and (2) work similarly in asynchronous logic, temporal masking will be very different: Instead of the rigid clock there is a flexible timing driven by completion detection. Preliminary investigations have revealed that skew plays a significant role here. Your task will be is a closer examination of this issue in both theory and practice: The masking effects shall be compared by their principles and determinating effects, and those effects shall be quantified for concrete practical examples (by means of simulations, demonstrators or timing analyses of existing designs), including electrical and logical masking.

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Confidence Analysis of a Fault Dictionary for Radiation Experiments

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Projektass.(FWF) MSc Varadan SAVULIMEDU VEERAVALLI, 07. 08. 2012

We are currently developing a target chip for an experimental analysis of the effect of radiation on VLSI circuits. Beyond the actual target circutis (basic functions like Muller C-elements, inverter chains, adders, ect.), this chip also comprises infrastructure for preprocesing and data collection. This infrastructure is also exposed to radiation and will therefore also experience upsets. Therefore it is equipped with redundancy and hence reports several views of the upset counts observed throughour a measurement period. We have already developed a fault dictionary that assigns to each set of reported count values the most probable physical scnario that caused it. However, there are always other, less probable scenarios that may lead to the same observation report. Your task will be a systematic analysis of the possible "less probable" interpretations, as well as a quantification of their relative probability. Based on these results our fault dictionary can then be enhanced by confidence values and further statistical characterization.

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Efficient Interfacing Between Timing Domains

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Bakk.techn. Robert NAJVIRT, Dipl.-Ing. Dr.techn. Thomas POLZER, 03. 10. 2012

Within a closed timing domain the setup/hold requirements of all stateful elements can be safely met. Examples are a globally synchronous clock domain or an asynchronous handshake domain. Often it is, however, necessary to exchange signals between two (or more) such timing domains, which inevidently leads to metastability problems at the interfaces.
Your task will be to compile and compare existing solutions for this problem (assumptions, overheads, throughput, upset rate,...), using analytic models and analog simulations. The whole matrix of interfaces between synchronous systems, bounded delay systems and delay insensitive systems shall be covered, considering the diverse levels of synchrony (mesochronous, plesiochronous) and the asynchropnous handshake protocols (2-phase, 4-phase). Where required, new solutions shall be developed, and existing ones be improved. Applicable tools for the proof of concept as well as the assessment of the solutions' properties are simulation and FPGA prototype implementation.

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Generic Bytecode Instrumentation with LLVM and InterAspect

CPS: Univ.Ass. Mag. Kenan KALAJDZIC, 24. 10. 2012

The goal of this Master’s thesis is to port the InterAspect program-instrumentation framework from GCC to LLVM, document the porting process and evaluate the implementation by means of realistic case studies.

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Dynamic Reconfiguration Framework

CPS: Univ.Ass. Dipl.-Ing. Oliver HÖFTBERGER, 10. 09. 2014

The aim of this project is to develop a dynamic reconfiguration framework that allows to
autonomously substitute faulty components in an embedded system.

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Optimizations for Time-predictable Code

CPS: Dipl.-Ing. BSc Daniel Leo WILTSCHE-PROKESCH, Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 01. 09. 2015

Design and to implement optimisations that are tailored to single-path code generation.

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Data-Cache Analysis for a Time-predictable Processor

CPS: Dipl.-Ing. BSc Daniel Leo WILTSCHE-PROKESCH, Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 01. 09. 2015

State-of-the-art and novel techniques for data cache analysis should be implemented in a compiler/worst-case execution time analysis framework for a time-predictable processor.

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Deciphering the C. Elegans “Brain”

CPS: Univ.Prof. Dipl.-Ing. Dr.rer.nat. Radu GROSU, 13. 10. 2015

Deep neural networks are nowadays one of the most active areas of research. Google, Apple, IBM and Microsoft are all on the hunt for people with expertise in this area. For example, Google bought in 2014 the startup DeepMind for $500 Million (see http://techcrunch.com/2014/01/26/google-deepmind/).

Unfortunately, the learned deep neural networks, although very effective in classification tasks, for example, remain more or less a black box. One cannot say for sure, what every neuron in the learned network does. This is one of the main obstacles for the wide acceptance of such networks. Scientists and engineers want to understand the systems they design, such that they are able to also make predictions about their future behavior.

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Self-organizing Flight Formations

CPS: Univ.Prof. Dipl.-Ing. Dr.rer.nat. Radu GROSU, 16. 02. 2016

Long distance migrating birds, such as geese, are often observed travelling in v-shaped formations. This coordinated flight allows birds flying in the back to exploit an effect called upwash. This upwash gives individuals, flying in the right spot behind another bird, an aero dynamical benefit. As a result these birds require less energy and in turn the entire flock is able to conserve energy and hence travel further.

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