Practicals & Theses

List of practicals and theses at the institute (see also TI Research Presentations)

IoT Distributed Consensus Algorithm Implementation

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, 25. 10. 2019

The goal of this Bachelor thesis, which can also be expanded to a Master thesis, is to implement and experimentally analyze the performance of a novel distributed consensus algorithm for dynamic networks.

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Predicting Analog Waveforms based on Digital Delay Estimation Schemes

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 08. 08. 2019

Simulating digital circuits at the analog level is a challenging and time-consuming task. To reduce simulation times, abstractions (primarily digital ones) are used that produce reasonably accurate results in a far less amount of time. The purpose of this assignment is the implementation of an analog abstraction and its experimental evaluation: Based on an existing digital delay estimation tool, which predicts when the analog waveform of a circuit hits a specific threshold voltage value, the analog waveform shall be approximated and compared to accurate analog simulations.

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Gate Parameter Impact on Delay and its Prediction

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 08. 08. 2019

Estimating the delay of a gate is a crucial task in digital circuit design. 
While the actual simulation is easy and quickly done, characterization still
consumes a lot of time and effort: Each gate has to be matched
separately, as the surroundings, which play an important role, differ almost
certainly between various gates of the same type. The goal of this assignment
is to experimentally determine the impact of certain parameters on the delay
and to come up with an appropriate prediction model.

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Loosening Bounds for Nondeterministic Delay Estimation

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 08. 08. 2019

Estimating the delay of a gate is a very crucial task in circuit
design. However, no matter how accurate the gate characterization is,
real circuits will always experience some manufacturing variations
and operating condition dependencies that lead to unpredictable
delay variations. We therefore augmented our novel involution delay
model by adding non-deterministic delay noise. Unfortunately, tight
bounds on the maximum variation had to be introduced in order to
retain the correctness properties of the model. The purpose of this
assignment is to relax these tight bounds, by exploiting the fact
that the delay noise primarily affects very short pulses in the
signal traces only.

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Experimental measurement of Schmitt Trigger Metastability

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 05. 07. 2019

Rather than assuming a stable HI or LO, digital storage elements can, under adverse conditions, also assume a so-called metastable state for some time. This undefined state creates problems in the subsequent logic. Quite unexpectedly, Schmitt Trigger circuits can also become metastable, even though their purpose is not data storage.

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Modelling of a Multistage Synchronizer

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 05. 07. 2019

At clock domain boundaries violation of setup- and hold time cannot be avoided. Synchronizers are used to mitigate the metastability that results from these violations. In modern technologies with their parameter variations and narrow timing margins, conventional single stage synchronizers are no more sufficient and need to be cascaded, thus forming multi-stage synchronizers. While theory provides a reasonably good estimation for the reliability (in terms of mean time between upsets, MTBU) of the single stage synchronizer, the MTBU estimation for the multi-stage synchronizer seems to be to simplistic. In particular, the influence of the input thresholds is currently not considered.

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Increasing Resilience of Schmitt Triggers against Metastability

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 05. 07. 2019

Schmitt Triggers, often used to block metastable voltages, can be driven into
metastability themselves. In detail it is possible to hold any voltage value between
ground and the supply voltage value at the output for an arbitrary amount of
time. To achieve these values gets however harder the faster the Schmitt Trigger
can operate, i.e., the higher the output derivatives gets. Of course this could
be achieved by scaling everything which is however not very beneficial. It is
therefore crucial to know which part of which component has a high impact on the
slope and just tune that parameter.

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Self-organizing Flight Formations

CPS: Univ.Prof. Dipl.-Ing. Dr.rer.nat. Radu GROSU, 16. 02. 2016

Long distance migrating birds, such as geese, are often observed travelling in v-shaped formations. This coordinated flight allows birds flying in the back to exploit an effect called upwash. This upwash gives individuals, flying in the right spot behind another bird, an aero dynamical benefit. As a result these birds require less energy and in turn the entire flock is able to conserve energy and hence travel further.

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Deciphering the C. Elegans “Brain”

CPS: Univ.Prof. Dipl.-Ing. Dr.rer.nat. Radu GROSU, 13. 10. 2015

Deep neural networks are nowadays one of the most active areas of research. Google, Apple, IBM and Microsoft are all on the hunt for people with expertise in this area. For example, Google bought in 2014 the startup DeepMind for $500 Million (see http://techcrunch.com/2014/01/26/google-deepmind/).

Unfortunately, the learned deep neural networks, although very effective in classification tasks, for example, remain more or less a black box. One cannot say for sure, what every neuron in the learned network does. This is one of the main obstacles for the wide acceptance of such networks. Scientists and engineers want to understand the systems they design, such that they are able to also make predictions about their future behavior.

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Optimizations for Time-predictable Code

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, Dipl.-Ing. BSc Daniel Leo WILTSCHE-PROKESCH, 01. 09. 2015

Design and to implement optimisations that are tailored to single-path code generation.

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Data-Cache Analysis for a Time-predictable Processor

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, Dipl.-Ing. BSc Daniel Leo WILTSCHE-PROKESCH, 01. 09. 2015

State-of-the-art and novel techniques for data cache analysis should be implemented in a compiler/worst-case execution time analysis framework for a time-predictable processor.

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Dynamic Reconfiguration Framework

CPS: Univ.Ass. Dipl.-Ing. Oliver HÖFTBERGER, 10. 09. 2014

The aim of this project is to develop a dynamic reconfiguration framework that allows to
autonomously substitute faulty components in an embedded system.

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Generic Bytecode Instrumentation with LLVM and InterAspect

CPS: Univ.Ass. Mag. Kenan KALAJDZIC, 24. 10. 2012

The goal of this Master’s thesis is to port the InterAspect program-instrumentation framework from GCC to LLVM, document the porting process and evaluate the implementation by means of realistic case studies.

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Camera Integration in Windows Embedded

CPS: Projektass. Dipl.-Ing. Dr.techn. Armin WASICEK, 04. 04. 2012

The goal of the Master's thesis is to develop a software to integrate video streams from three different cameras in Windows Embedded Compact 7. A special application (which is already available for Desktop Windows) will run several image processing algorithms on the captured video streams. This existing application uses DirectShow which is not available under Windows Embedded. Therefore a similar functionality has to be implemented.

The thesis will be carried out as an "Industrie-Diplomarbeit" together with an industrial company. A funding will be provided by the company.

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Compilation for Predictable Real-Time Systems

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 01. 03. 2010

Usually, the focus of compiler writers is to generate fast code. Contrasting this, the goal of this thesis is to work on code generation strategies that produce code with predictable timing, i.e., the stability of the timing and a simple prediction of the worst-case execution time are in the center of interest.

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Worst-Case Execution-Time Analysis Tool for ARM Processor

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 31. 03. 2009

In this project students develop a worst-case execution-time analysis tool for an ARM7 micro controller board.

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TTNoC boundary test with interleaved messages (New, exciting, and promising!)

CPS: Dipl.-Ing. Harald PAULITSCH, 12. 02. 2009

Masterarbeit ::: Seminar mit Bachelorarbeit + Projektpraktikum ::: Building on the Unique Selling Proposition of time-triggered systems, the predictability, interleave test messages with regular traffic to iteratively identify and ultimately pinpoint faulty network links.

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Design of a Repository for Embedded Real Time Applications

CPS: Sven BÜNTE, 10. 11. 2008

The FORmal Timing Analysis Suite is a framework for the validation of temporal requirements in the context of embedded real time systems. In cooperation with TU Darmstadt and partners from industry we are currently developing a tool that automatically provides timing properties for software and system architects.

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Implementation of a Measurement Framework for WCET Analysis Tools

CPS: Sven BÜNTE, 24. 04. 2008

Several processor types are used in the embedded domain, each of them demanding specific strategies to perform temporal measurements. The goal is to conveniently implement extensions of a framework that unifies some of these strategies. Strong programming skills in C++ are a requisite. Knowledge of MS Visual Studio and software engineering in general is beneficial.

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Development of a Timing Analysis Tool for a specific Hardware Platform

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006

The task is to develop a timing analysis tool that allows to calculate the maximum execution time of real-time programs. The part of the tool to calculate the execution time already exists. What has to be done is to add a front end that can read assembly code or object code and construct and to build a timing model for a specific processor (Motorola MC68k or PPC, ARM, ...)

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Concepts of Execution Time Analysis studied on the Linux Kernel

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006

By using the source code of the Linux kernel one should analyse, what constructs or mechanisms could influence the timing behavior of the operating system. Optionally, the analysis could be done using Real-Time Linux as a case study.

The analysis should cover synchronisation mechanisms as well as scheduling techniques.

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Formal Specification of Real-Time Systems

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006

Within the project TeDES we have a research cooperation with industrial partners from the automotive industry to develop a test environment to systematically verify distributed safety-critical real-time systems.

Within this Masther's thesis one will work on model-based testing, with the focus on formal mechanisms for specifying real-time systems. Formal means, that the description has a well-defined meaning.

The aim of this work is to remove or reduce the error-prone and tedios process of generating test cases manually. This work is also of high practical significance in industry.

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Limitations on the Analyzability of Real-Time Systems

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006

To operate real-time sytems in a safe way, it is required to know the maximum execution time of the program code. However, there are problems to reason about the program behavior in general (c.f., the Halting Problem).


It is the goal of this work to analyze the problem from the other side, i.e., by analyzing what code structures are predictable. For this one has to also look on program analysis methods to reason about what properties can be derived by such an analysis. It is the goal of this work to find restrictions on the program structures, such that the execution time analysis becomes feasible.

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Safety-Requirements to Validate Real-Time Systems

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006

Within the project TeDES we have a research cooperation with industrial partners from the automotive industry to develop a test environment to systematically verify distributed safety-critical real-time systems.

Within this Masther's thesis one should study existing safety requirements on their impact on the systematic testing of real-time systems. The goal is to obtain a framework to specify test scenarious for the systematic test of distributed real-time systems.

The aim of this work is to remove or reduce the error-prone and tedios process of generating test cases manually. This work is also of high practical significance in industry.

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Assigned Practicals

Approximating Analog Waveforms by adding Arbitrary Functions

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 08. 08. 2019

Tracing the analog behavior of a digital circuit is a very challenging task
and thus also very time consuming. To reduce simulation time, abstractions are
introduced that yield only slightly less accuracy in far less amount of
time. One example is to use rising and falling transitions of a certain function
family, e.g. sigmoids, and create pulses by properly adding these. It has
already been shown that this approach works well, however, until now no
qualified matching between input and output pulses could be established that
would enable a very simple and accurate analog estimation suite.

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4 vs 2 phase Logic Design

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 05. 07. 2019

A general rule of thumb in asynchronous circuit design says that the 4-phase protocol is used for computation while the 2-phase one is used for communication. The reason is that 4-phase gates are smaller in size while the 2-phase protocol allows higher speed. The question that has however not yet been answered is the actual amount of the deviation. How much bigger are 2-phase gates compared to 4-phase? How much faster are they? This thesis therefore focuses on comparing different 2- and 4-phase implementations analytically and on an FPGA. Based on the achieved results the design of novel and innovative gates might become possible.

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Automatic Verification Framework of VHDL Code examples

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 05. 07. 2019

In the lecture Hardware Modeling training examples are provided via TUWEL
however it is not possible for the students to check if their solution is
working correctly. Therefore a framework is desired that accepts a piece of
code, runs test benches and reports the result back to the user. The used
procedure thereby has to satisfy the DSGVO and a certain level of security.

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[assigned] Implementation of Pointer Authentication on a 32-bit RISC-V CPU

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Stefan TAUNER, 05. 07. 2019

Pointer Authentication (PA) is a method to strengthen the resilience of computer systems against attacks exploiting memory corruption. If an attacker is able to redirect pointers she might gain control about the execution flow eventually. Pointer Authentication is able to detect such modifications from unauthorized places in the code and thus thwart the malign consequences.

Industry has taken up this idea already from academia and is adding support to new implementations of existing microarchitectures (e.g., on ARMv8.3).

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Efficient Interfacing Between Timing Domains

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Bakk.techn. Robert NAJVIRT, Dipl.-Ing. Dr.techn. Thomas POLZER, 03. 10. 2012

Within a closed timing domain the setup/hold requirements of all stateful elements can be safely met. Examples are a globally synchronous clock domain or an asynchronous handshake domain. Often it is, however, necessary to exchange signals between two (or more) such timing domains, which inevidently leads to metastability problems at the interfaces.
Your task will be to compile and compare existing solutions for this problem (assumptions, overheads, throughput, upset rate,...), using analytic models and analog simulations. The whole matrix of interfaces between synchronous systems, bounded delay systems and delay insensitive systems shall be covered, considering the diverse levels of synchrony (mesochronous, plesiochronous) and the asynchropnous handshake protocols (2-phase, 4-phase). Where required, new solutions shall be developed, and existing ones be improved. Applicable tools for the proof of concept as well as the assessment of the solutions' properties are simulation and FPGA prototype implementation.

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Autonomous-Car Simulator

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 31. 03. 2009

Within this project students develop a simulator for an autonomous model car that has to follow a given course.

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Algorithms with Stable Timing

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 31. 03. 2009

The goal of this thesis project is to develop new algorithms characterized by stable timing for a number of programming problems.

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Visualization of Process Synchronization

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 30. 03. 2009

The goal of this project is to develop simulation software to illustrate the synchronization of processes via semaphores and illustrate deadlock behaviour.

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WCET Analysis of Java Applications

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Martin SCHÖBERL, 13. 03. 2006

Worst-case execution time (WCET) estimates are essential for real-time systems. The theory for static WCET analysis is mature. However, the tools are still missing. The tool shall provide WCET estimates for Java real-time applications running on a Java processor (JOP) that is designed to be an easy target for WCET analysis.

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Predictable Cache Memory

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 10. 03. 2006

Cache memories are used to boost the performance of computer memory systems. While the performance benefit of caches is indeed substantial, the use of caches makes the calculation of the run times of code very difficult. The goal of this work is therefore to conceive a new type of hierarchical memory system, that allows for both, a high performance of program execution and a good predictability of code timing.

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