Practicals & Theses
List of practicals and theses at the institute (see also TI Research Presentations)
Implementation of delay-encoded spiking neural network links
ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, 07. 03. 2023
Delay encoding is a power-efficient alternative to frequency encoding for implementing spiking neural network links, which are needed for communicating analog values between neurons. The goal of this assignment is to come up with a light-weight asynchronous implementation of such a link, and its experimental evaluation using digital and analog simulations.
Gate Delay Characterization
ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, 08. 08. 2019
Estimating the delay of a gate is a crucial task in digital circuit design. Whereas it is relatively easy to measure characteristic gate delay values like worst-case rising and falling transition delays via simulations, the question of determining these values for all the gates in a circuit without individual measurements. After all, both the surroundings of a gate (like load capacitance and interconnect characteristics) and operating conditions (like supply voltage and input slewrate) have a severe impact on gate delays. Models like CCSM and ECSM used in static timing analysis do a very good job for determining worst-case delays, but cannot provide all characteristic delay values of interest. The goal of this assignment is to explore ways to accomplish this.
Experimental measurement of Schmitt Trigger Metastability
ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 05. 07. 2019
Rather than assuming a stable HI or LO, digital storage elements can, under adverse conditions, also assume a so-called metastable state for some time. This undefined state creates problems in the subsequent logic. Quite unexpectedly, Schmitt Trigger circuits can also become metastable, even though their purpose is not data storage.
Modelling of a Multistage Synchronizer
ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 05. 07. 2019
At clock domain boundaries violation of setup- and hold time cannot be avoided. Synchronizers are used to mitigate the metastability that results from these violations. In modern technologies with their parameter variations and narrow timing margins, conventional single stage synchronizers are no more sufficient and need to be cascaded, thus forming multi-stage synchronizers. While theory provides a reasonably good estimation for the reliability (in terms of mean time between upsets, MTBU) of the single stage synchronizer, the MTBU estimation for the multi-stage synchronizer seems to be to simplistic. In particular, the influence of the input thresholds is currently not considered.
Increasing Resilience of Schmitt Triggers against Metastability
ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 05. 07. 2019
Schmitt Triggers, often used to block metastable voltages, can be driven into
metastability themselves. In detail it is possible to hold any voltage value between
ground and the supply voltage value at the output for an arbitrary amount of
time. To achieve these values gets however harder the faster the Schmitt Trigger
can operate, i.e., the higher the output derivatives gets. Of course this could
be achieved by scaling everything which is however not very beneficial. It is
therefore crucial to know which part of which component has a high impact on the
slope and just tune that parameter.
Simulation of a Quadcopter with Matlab
CPS: Univ.Ass. Dipl.-Ing. BSc Denise RATASICH, 26. 02. 2016
<span id="thesisForm:description">An autonomously controlled quadcopter should be simulated and visualized in a 3D world. Various simulation environments shall be explored and the most suitable framework selected for implementation.</span>
Modellierung und Redundanz eines zeitgesteuerten CAN Routers
CPS: Dipl.-Ing. Roland KAMMERER, 25. 04. 2012
Derzeit wird an unserem Institut ein Prototyp eines zeitgesteuerten CAN-Routers entwickelt (Ref: 1). Die im Paper angesprochenen positiven Eigenschaften wurden durch Messungen auf einer Prototyphardware bestätigt. Ihre Aufgaben umfassen folgende Tätigkeiten:
*) Modellierung des CAN-Routers mit Hilfe von Matlab/Simulink und TrueTime (Ref: 2). Eine Proof-of-Concept Implementierung ist vorhanden, muss aber verfeinert/ausgebaut werden. Die Einstiegshürde von TrueTime ist relativ gering. Erfahrungen mit TrueTime sind nicht notwendig.
*) Abbildung/Durchführung von ausgewählten Testszenarien in diesem Modell, um die Resultate des Modells mit der Prototypimplementierung vergleichen zu können.
*) Der Hauptteil der Arbeit umfasst die Erweiterung des Modells um eine zweite, redundante CAN-Router Komponente. In diesem Teil soll der momentane Single-Point-of-Failure (ein einzelner Router) durch ein redundantes Routersetup ersetzt werden. Vor allem dieser Punkt bietet Einblick in interessante Aufgabenstellungen zeitgesteuerter Systeme (z.B.: Synchronisation von zeitgesteuerten Systemen, Fehlertoleranz, Agreement-Protokolle,...)
(Ref: 1) Abstract:
Controller Area Network (CAN) provides an inexpensive and robust network technology in many application domains. However, the use of CAN is constrained by limitations with respect to fault isolation, bandwidth, wire length, namespaces and diagnosis. This paper presents a solution to overcome these limitations by replacing the CAN bus with a star topology. We introduce a CAN router that detects and isolates node failures in the value and time domain. The CAN router ensures that minimum message interarrival times are satisfied and reserves CAN identifiers for individual CAN nodes. In addition, the CAN router exploits knowledge about communication relationships for a more efficient use of communication bandwidth through multicast messaging. An implementation of the CAN router based on a Multi-Processor System-on-a-Chip (MPSoC) shows the feasibility of the proposed solution.
(Ref: 1) http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5549449&contentType=Conference+Publications&sortType%3Dasc_p_Sequence%26filter%3DAND(p_IS_Number%3A5549388)
(Ref: 2) http://www3.control.lth.se/truetime/
Tool zur Analyse von Messdatenreihen
CPS: Projektass. Dipl.-Ing. Dr.techn. Armin WASICEK, 22. 12. 2011
Ziel des Praktikums ist es ein Tool in Visual Basic als Erweiterung für Excel zu erstellen, das Wissenschafter in der Analyse von Messdaten unterstützt. Momentan wird der zeitliche Abgleich verschiedener Messdaten manuell durchgeführt. Das Tool soll diese Vorgehensweise automatisieren. Das Praktikum ist eine Kooperation mit dem Institut für Verfahrenstechnik und Biowissenschaft.
Neue Wege und Methoden fuer die SIMULINK Visualisierung und Interaktion von komplexen Systemen
CPS: Projektass. Dipl.-Ing. Dr.techn. Christian EL-SALLOUM, 02. 07. 2009
SIMULINK und MATLAB sind ein mächtiges Mathematik Toolset mit einem reichhaltigen Satz an wissenschaftlichen Bibliotheken. Sie erfreuen sich einer breiten Marktpenetration im wissenschaftlichen und R&D Bereich. Momentan ist das Toolset Marktführer in den Bereichen für Simulation angefangen von Automotive, Aerospace, Finanz bis hin zu chemischen Prozessen.
Viele existierenden SIMULINK und MATLAB Visualisierungsmethoden/Interaktionsmethoden sind stark mathematisch motiviert, bieten aber nicht ausreichend integrierte Mechanismen für eine simple, intuitive und erweiterbare Visualisierung im nicht mathematischen Bereich für Anwender aus anderen Fachgebieten außer der Informatik oder der Mathematik. Darüber hinaus haben Anwender aus anderen Domänen einen anderen Bedarf an Feedback aufgrund einer differenzierten Problemperspektive welche SIMULINK und MATLAB aufgrund Ihres Designs nicht abdecken kann.
Für Endbenutzer ist nicht nur die Funktionalität eines Systems und dessen Ausgaben von Bedeutung sondern auch die Möglichkeit einer intuitiven und flexiblen graphischen Interaktion. Die führende Toolkette für Visualisierung und Interaktion ist das Adobe Produktset „Adobe Flash“ mit einer Marktpenetration von 99% im Browsersektor und einer hohen Verfügbarkeit auf gängigen Plattformen.
Aufgabe:
Ziel ist es ein "Glue" Code Interface zu erstellen welches SIMULINK mit Adobe Flash integriert.
Worst-Case Execution-Time Analysis Tool for ARM Processor
CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 31. 03. 2009
In this project students develop a worst-case execution-time analysis tool for an ARM7 micro controller board.
Visualization of Disk Scheduling Policies
CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 30. 03. 2009
The goal of this project is to write simulation software that illustrates the operation of different disk scheduling strategies.
TTNoC boundary test with interleaved messages (New, exciting, and promising!)
CPS: Dipl.-Ing. Harald PAULITSCH, 12. 02. 2009
Masterarbeit ::: Seminar mit Bachelorarbeit + Projektpraktikum ::: Building on the Unique Selling Proposition of time-triggered systems, the predictability, interleave test messages with regular traffic to iteratively identify and ultimately pinpoint faulty network links.
Design of a Repository for Embedded Real Time Applications
CPS: Sven BÜNTE, 10. 11. 2008
The FORmal Timing Analysis Suite is a framework for the validation of temporal requirements in the context of embedded real time systems. In cooperation with TU Darmstadt and partners from industry we are currently developing a tool that automatically provides timing properties for software and system architects.
Implementation of a Measurement Framework for WCET Analysis Tools
CPS: Sven BÜNTE, 24. 04. 2008
Several processor types are used in the embedded domain, each of them demanding specific strategies to perform temporal measurements. The goal is to conveniently implement extensions of a framework that unifies some of these strategies. Strong programming skills in C++ are a requisite. Knowledge of MS Visual Studio and software engineering in general is beneficial.
Development of a Timing Analysis Tool for a specific Hardware Platform
CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006
The task is to develop a timing analysis tool that allows to calculate the maximum execution time of real-time programs. The part of the tool to calculate the execution time already exists. What has to be done is to add a front end that can read assembly code or object code and construct and to build a timing model for a specific processor (Motorola MC68k or PPC, ARM, ...)
Concepts of Execution Time Analysis studied on the Linux Kernel
CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006
By using the source code of the Linux kernel one should analyse, what constructs or mechanisms could influence the timing behavior of the operating system. Optionally, the analysis could be done using Real-Time Linux as a case study.
The analysis should cover synchronisation mechanisms as well as scheduling techniques.
Execution Time Analysis of Matlab/Simulink Programs
CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006
A tool should be developed that allows to calculate the maximum loop iteration counts of program autmatically generated from Matlab/Simulink models. The analysis is feasible, because the code generated out of Matlab/Simulink models has typically a relative simple structure.
After the loop analysis the tool should call an existing timing analysis tool to calculate the maximum execution time and map it back to blocks in Matlab/Simulink.
Assigned Practicals
Automatic Verification Framework of VHDL Code examples
ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 05. 07. 2019
In the lecture Hardware Modeling training examples are provided via TUWEL
however it is not possible for the students to check if their solution is
working correctly. Therefore a framework is desired that accepts a piece of
code, runs test benches and reports the result back to the user. The used
procedure thereby has to satisfy the DSGVO and a certain level of security.
4 vs 2 phase Logic Design
ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 05. 07. 2019
A general rule of thumb in asynchronous circuit design says that the 4-phase protocol is used for computation while the 2-phase one is used for communication. The reason is that 4-phase gates are smaller in size while the 2-phase protocol allows higher speed. The question that has however not yet been answered is the actual amount of the deviation. How much bigger are 2-phase gates compared to 4-phase? How much faster are they? This thesis therefore focuses on comparing different 2- and 4-phase implementations analytically and on an FPGA. Based on the achieved results the design of novel and innovative gates might become possible.
Battery Management
CPS: Univ.Ass. Dipl.-Ing. BSc Denise RATASICH, 30. 06. 2015
The aim of this project is to develop a small battery management unit for one of our mobile robots.
Aufbau eines CAN Systems (Lötpraktikum)
CPS: Projektass. Dipl.-Ing. Dr.techn. Armin WASICEK, 22. 02. 2011
Ziel des Praktikums ist es ein CAN System mit AVR Mikrocontrollern aufzubauen.
Visualization of Process Synchronization
CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 30. 03. 2009
The goal of this project is to develop simulation software to illustrate the synchronization of processes via semaphores and illustrate deadlock behaviour.
Java bytecode optimizer
CPS: Privatdoz. Dipl.-Ing. Dr.techn. Martin SCHÖBERL, 13. 03. 2006
The standard Java compiler (javac) performs no optimization at all. Optimization is postboned to the JIT compiler. For a Java processor (or an interpreting JVM) this is not an optimal solution. The idea is to implement standard compiler optimizations and processor specific optimizations at the bytecode level. See: JVM Specification, Byte Code Engineering Library and ASM