Practicals & Theses

List of practicals and theses at the institute (see also TI Research Presentations)

Development of a Timing Analysis Tool for a specific Hardware Platform

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006

The task is to develop a timing analysis tool that allows to calculate the maximum execution time of real-time programs. The part of the tool to calculate the execution time already exists. What has to be done is to add a front end that can read assembly code or object code and construct and to build a timing model for a specific processor (Motorola MC68k or PPC, ARM, ...)

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Concepts of Execution Time Analysis studied on the Linux Kernel

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006

By using the source code of the Linux kernel one should analyse, what constructs or mechanisms could influence the timing behavior of the operating system. Optionally, the analysis could be done using Real-Time Linux as a case study.

The analysis should cover synchronisation mechanisms as well as scheduling techniques.

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Execution Time Analysis of Matlab/Simulink Programs

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Raimund KIRNER, 08. 03. 2006

A tool should be developed that allows to calculate the maximum loop iteration counts of program autmatically generated from Matlab/Simulink models. The analysis is feasible, because the code generated out of Matlab/Simulink models has typically a relative simple structure.

After the loop analysis the tool should call an existing timing analysis tool to calculate the maximum execution time and map it back to blocks in Matlab/Simulink.

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Java bytecode optimizer

CPS: Privatdoz. Dipl.-Ing. Dr.techn. Martin SCHÖBERL, 13. 03. 2006

The standard Java compiler (javac) performs no optimization at all. Optimization is postboned to the JIT compiler. For a Java processor (or an interpreting JVM) this is not an optimal solution. The idea is to implement standard compiler optimizations and processor specific optimizations at the bytecode level. See: JVM Specification, Byte Code Engineering Library and ASM

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Implementation of a Measurement Framework for WCET Analysis Tools

CPS: Sven BÜNTE, 24. 04. 2008

Several processor types are used in the embedded domain, each of them demanding specific strategies to perform temporal measurements. The goal is to conveniently implement extensions of a framework that unifies some of these strategies. Strong programming skills in C++ are a requisite. Knowledge of MS Visual Studio and software engineering in general is beneficial.

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Design of a Repository for Embedded Real Time Applications

CPS: Sven BÜNTE, 10. 11. 2008

The FORmal Timing Analysis Suite is a framework for the validation of temporal requirements in the context of embedded real time systems. In cooperation with TU Darmstadt and partners from industry we are currently developing a tool that automatically provides timing properties for software and system architects.

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TTNoC boundary test with interleaved messages (New, exciting, and promising!)

CPS: Dipl.-Ing. Harald PAULITSCH, 12. 02. 2009

Masterarbeit ::: Seminar mit Bachelorarbeit + Projektpraktikum ::: Building on the Unique Selling Proposition of time-triggered systems, the predictability, interleave test messages with regular traffic to iteratively identify and ultimately pinpoint faulty network links.

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Visualization of Process Synchronization

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 30. 03. 2009

The goal of this project is to develop simulation software to illustrate the synchronization of processes via semaphores and illustrate deadlock behaviour.

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Visualization of Disk Scheduling Policies

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 30. 03. 2009

The goal of this project is to write simulation software that illustrates the operation of different disk scheduling strategies.

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Worst-Case Execution-Time Analysis Tool for ARM Processor

CPS: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Peter PUSCHNER, 31. 03. 2009

In this project students develop a worst-case execution-time analysis tool for an ARM7 micro controller board.

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Neue Wege und Methoden fuer die SIMULINK Visualisierung und Interaktion von komplexen Systemen

CPS: Projektass. Dipl.-Ing. Dr.techn. Christian EL-SALLOUM, 02. 07. 2009

SIMULINK und MATLAB sind ein mächtiges Mathematik Toolset mit einem reichhaltigen Satz an wissenschaftlichen Bibliotheken. Sie erfreuen sich einer breiten Marktpenetration im wissenschaftlichen und R&D Bereich. Momentan ist das Toolset Marktführer in den Bereichen für Simulation angefangen von Automotive, Aerospace, Finanz bis hin zu chemischen Prozessen.

Viele existierenden SIMULINK und MATLAB Visualisierungsmethoden/Interaktionsmethoden sind stark mathematisch motiviert, bieten aber nicht ausreichend integrierte Mechanismen für eine simple, intuitive und erweiterbare Visualisierung im nicht mathematischen Bereich für Anwender aus anderen Fachgebieten außer der Informatik oder der Mathematik. Darüber hinaus haben Anwender aus anderen Domänen einen anderen Bedarf an Feedback aufgrund einer differenzierten Problemperspektive welche SIMULINK und MATLAB aufgrund Ihres Designs nicht abdecken kann.

Für Endbenutzer ist nicht nur die Funktionalität eines Systems und dessen Ausgaben von Bedeutung sondern auch die Möglichkeit einer intuitiven und flexiblen graphischen Interaktion. Die führende Toolkette für Visualisierung und Interaktion ist das Adobe Produktset „Adobe Flash“ mit einer Marktpenetration von 99% im Browsersektor und einer hohen Verfügbarkeit auf gängigen Plattformen.

Aufgabe:
Ziel ist es ein "Glue" Code Interface zu erstellen welches SIMULINK mit Adobe Flash integriert.

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Aufbau eines CAN Systems (Lötpraktikum)

CPS: Projektass. Dipl.-Ing. Dr.techn. Armin WASICEK, 22. 02. 2011

Ziel des Praktikums ist es ein CAN System mit AVR Mikrocontrollern aufzubauen.

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Tool zur Analyse von Messdatenreihen

CPS: Projektass. Dipl.-Ing. Dr.techn. Armin WASICEK, 22. 12. 2011

Ziel des Praktikums ist es ein Tool in Visual Basic als Erweiterung für Excel zu erstellen, das Wissenschafter in der Analyse von Messdaten unterstützt. Momentan wird der zeitliche Abgleich verschiedener Messdaten manuell durchgeführt. Das Tool soll diese Vorgehensweise automatisieren. Das Praktikum ist eine Kooperation mit dem Institut für Verfahrenstechnik und Biowissenschaft.

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Modellierung und Redundanz eines zeitgesteuerten CAN Routers

CPS: Dipl.-Ing. Roland KAMMERER, 25. 04. 2012

Derzeit wird an unserem Institut ein Prototyp eines zeitgesteuerten CAN-Routers entwickelt (Ref: 1). Die im Paper angesprochenen positiven Eigenschaften wurden durch Messungen auf einer Prototyphardware bestätigt. Ihre Aufgaben umfassen folgende Tätigkeiten:

*) Modellierung des CAN-Routers mit Hilfe von Matlab/Simulink und TrueTime (Ref: 2). Eine Proof-of-Concept Implementierung ist vorhanden, muss aber verfeinert/ausgebaut werden. Die Einstiegshürde von TrueTime ist relativ gering. Erfahrungen mit TrueTime sind nicht notwendig.

*) Abbildung/Durchführung von ausgewählten Testszenarien in diesem Modell, um die Resultate des Modells mit der Prototypimplementierung vergleichen zu können.

*) Der Hauptteil der Arbeit umfasst die Erweiterung des Modells um eine zweite, redundante CAN-Router Komponente. In diesem Teil soll der momentane Single-Point-of-Failure (ein einzelner Router) durch ein redundantes Routersetup ersetzt werden. Vor allem dieser Punkt bietet Einblick in interessante Aufgabenstellungen zeitgesteuerter Systeme (z.B.: Synchronisation von zeitgesteuerten Systemen, Fehlertoleranz, Agreement-Protokolle,...)

(Ref: 1) Abstract:
Controller Area Network (CAN) provides an inexpensive and robust network technology in many application domains. However, the use of CAN is constrained by limitations with respect to fault isolation, bandwidth, wire length, namespaces and diagnosis. This paper presents a solution to overcome these limitations by replacing the CAN bus with a star topology. We introduce a CAN router that detects and isolates node failures in the value and time domain. The CAN router ensures that minimum message interarrival times are satisfied and reserves CAN identifiers for individual CAN nodes. In addition, the CAN router exploits knowledge about communication relationships for a more efficient use of communication bandwidth through multicast messaging. An implementation of the CAN router based on a Multi-Processor System-on-a-Chip (MPSoC) shows the feasibility of the proposed solution.

(Ref: 1) http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5549449&contentType=Conference+Publications&sortType%3Dasc_p_Sequence%26filter%3DAND(p_IS_Number%3A5549388)
(Ref: 2) http://www3.control.lth.se/truetime/

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Confidence Analysis of a Fault Dictionary for Radiation Experiments

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Projektass.(FWF) MSc Varadan SAVULIMEDU VEERAVALLI, 07. 08. 2012

We are currently developing a target chip for an experimental analysis of the effect of radiation on VLSI circuits. Beyond the actual target circutis (basic functions like Muller C-elements, inverter chains, adders, ect.), this chip also comprises infrastructure for preprocesing and data collection. This infrastructure is also exposed to radiation and will therefore also experience upsets. Therefore it is equipped with redundancy and hence reports several views of the upset counts observed throughour a measurement period. We have already developed a fault dictionary that assigns to each set of reported count values the most probable physical scnario that caused it. However, there are always other, less probable scenarios that may lead to the same observation report. Your task will be a systematic analysis of the possible "less probable" interpretations, as well as a quantification of their relative probability. Based on these results our fault dictionary can then be enhanced by confidence values and further statistical characterization.

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Synchronization of Inputs into an Asynchronous Timing Domain

ECS: Dipl.-Ing. Dr.techn. Thomas POLZER, Dipl.-Ing. Dr.techn. Andreas STEININGER, 24. 08. 2012

Asynchronous circuits do not have a rigid clock signal, but still their operation is cyclic, and sometimes there is a need to synchronize external input signals to these cycles of operation. The function required for this purpose is similar to that of a synchronizer in the classical synchronous systems. In general, a Muller C-Element (or a chain thereof) or an arbiter can be used for this purpose.
Your task will be to compare these two options. For this purpose you will develop transistor-level simulation models (in SPICE) for both variants and perform comparisons with respect to residual upset rate, area, power consumption, latency etc. In addition it may turn out useful to develop analytical models to allow for a more direct and generic comparison.

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Implementation Styles for Asynchronous Data Pipelines

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Bakk.techn. Robert NAJVIRT, 19. 10. 2012

Asynchronous Pipelines are typically controlled by a so-called Muller-Pipeline that handles the flow control in an elastic way. The control singnals created by the Muller-Pipeline are then connected to storage elements (registers) in order to manage the data flow appropriately. There are, however, many ways of doing this; like using both clock edges or just one, using flip flops or latches, by 4-phase or 2-phase protocol etc.
Your task will be to review the state of the art in this field, encompassing both bundled-data as well as quasi-delay insensitive pipelines. The result will be a comprehensive compilation of the methods, with each method being associated with the related pros and cons, preferred application cases as well as references and use cases from the literature. In the practical part of this work you will implement the methods and compare their performance, area overheads energy consumption etc.

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Evaluation of operating systems for microcontrollers in wireless embedded systems

ECS: Projektass.(FWF) Dipl.-Ing. BSc Martin PERNER, 30. 01. 2014

The scope of this work is to evaluate the difference between operating systems, e.g., TinyOS and contiki, on battery powered AT86RF230 RCB motes, with regards to performance, code size and architectural design style.

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Battery Management

CPS: Univ.Ass. Dipl.-Ing. BSc Denise RATASICH, 30. 06. 2015

The aim of this project is to develop a small battery management unit for one of our mobile robots.

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Development of a VxWorks Board Support Package for the Pandaboard

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, 23. 10. 2015

VxWorks (WindRiver) is a very popular real-time operating system for embedded platforms. The purpose of this project is to develop a Board Support Package (BSP) for the popular "Pandaboard" (http://www.omappedia.org/wiki/PandaBoard), which is based on the Texas Instruments OMAP 4430 processor (dual-core ARM9). The development can start from the existing Linux-BSP for the Pandaboard and the existing VxWorks BSPs for OMAP3-based platforms.

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Simulation of a Quadcopter with Matlab

CPS: Univ.Ass. Dipl.-Ing. BSc Denise RATASICH, 26. 02. 2016

<span id="thesisForm:description">An autonomously controlled quadcopter should be simulated and visualized in a 3D world. Various simulation environments shall be explored and the most suitable framework selected for implementation.</span>

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