Practicals & Theses

List of practicals and theses at the institute (see also TI Research Presentations)

Details for Are complex CPUs buggier?

In this Bachelor Thesis errata describing faults in commercial CPUs shall be analyzed.

Description

Modern CPUs comprise billions of transistors and thousands of complex logical units interacting with each other.
Due to the high costs of manufacturing verification is an important step in the design process.
However, it is neither cost-effective nor really feasible to discover all faults before manufacturing and thus bugs slip into hardware.
These may then be detected by the manufacturer during validation or discovered later by customers, users or researchers (or lie dormant forever).
Since fixing such errors with microcode and similar update mechanisms is very limited, corrections have to be employed via software workarounds.
Hardware vendors release documents called errata to specify unwanted behavior, circumstances that lead to it and possible ways for mitigation.

In this Bachelor Thesis errata describing faults in commercial CPUs shall be analyzed.
The research questions we propose for this project are as follows:

- Do published errata support the claim that increased complexity of CPUs increase the number of (detected) faults?
- How are the different kinds of faults distributed and how did this composition change over time?
- How do different market environments and use cases (e.g., general purpose CPUs vs. microcontrollers) influence errata publication?
- Can data from previous errata predict (the number and nature of) faults in future designs?

You need to define metrics and find data for the levels of complexity, fault severeness etc. to allow for proper statistical analyses.
To that end it will be necessary to delve into errata from multiple vendors published over the last few years and analyze them accordingly.
A similar work published about 20 years ago might be used as inspiration: Microprocessor Entomology: A Taxonomy of Design Faults in COTS Microprocessors

For any questions please contact Stefan Tauner.

Required Skills

At least basic knowledge about chip manufacturing and computer architectures are definitely advantageous when working on this project.

Supervisors

Dipl.-Ing. Dr.techn. Andreas STEININGER
E-Mail:
Homepage: https://ti.tuwien.ac.at/ecs/people/steininger/view

Univ.Ass. Dipl.-Ing. Stefan TAUNER (main responsibility)
E-Mail:

Types

Praktikum, Seminar

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