Practicals & Theses

List of practicals and theses at the institute (see also TI Research Presentations)

Details for Gate Parameter Impact on Delay and its Prediction

Estimating the delay of a gate is a crucial task in digital circuit design. 
While the actual simulation is easy and quickly done, characterization still
consumes a lot of time and effort: Each gate has to be matched
separately, as the surroundings, which play an important role, differ almost
certainly between various gates of the same type. The goal of this assignment
is to experimentally determine the impact of certain parameters on the delay
and to come up with an appropriate prediction model.

Description

Your task would be to conduct analog SPICE simulations on various gates to
derive delay functions for our involution delay model (can be fully automized)
and then compare the results. What impact do single changes like the input
slope, output capacitance and many others have? How can they be predicted? There
is also the conjecture that all delay function can be reasonably
determined by knowing three points of its graph. A nice outcome of this
work would be to falsify this assumption (or not falsifying it).

Required Skills

VO Digital Design, Transistor Behavior
VU Introduction to Programming 1/2

Supervisors

Dipl.-Ing. Dr.techn. Ulrich SCHMID
E-Mail:
Homepage: https://ti.tuwien.ac.at/ecs/people/schmid/view

Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER (main responsibility)
E-Mail:
Homepage: https://ti.tuwien.ac.at/ecs/people/jmaier

Types

Praktikum, Diplomarbeit

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