Practicals & Theses

List of practicals and theses at the institute (see also TI Research Presentations)

Details for Gate Delay Characterization

Estimating the delay of a gate is a crucial task in digital circuit design. Whereas it is relatively easy to measure characteristic gate delay values like worst-case rising and falling transition delays via simulations, the question of determining these values for all the gates in a circuit without individual measurements. After all, both the surroundings of a gate (like load capacitance and interconnect characteristics) and operating conditions (like supply voltage and input slewrate) have a severe impact on gate delays. Models like CCSM and ECSM used in static timing analysis do a very good job for determining worst-case delays, but cannot provide all characteristic delay values of interest. The goal of this assignment is to explore ways to accomplish this.


Your task would be to contemplate ways to develop a model for determining other characteristic delay values of interest from existing delay models, library data, technology information etc., and to validate your model by means of analog SPICE simulations.

Required Skills

Digital circuit design, analog simulations


Dipl.-Ing. Dr.techn. Ulrich SCHMID (main responsibility)


Praktikum, Diplomarbeit