Practicals & Theses

List of practicals and theses at the institute (see also TI Research Presentations)

Details for Porting of a RISC-V soft-core SoC (PULPissimo) to another FPGA platform

PULPissimo is the improved successor of PULPino, which is an open-source SoC platform implementing a RISC-V-based microcontroller.
This family of processors was developed by the ETH Zürich and the University of Bologna as part of the PULP project: https://pulp-platform.org
The main focus of PULPissimo's development so far was on simulation and ASIC implementations. However, there also exists an implementation of PULPissimo for a Digilent Genesys 2 FPGA development board (hosting a Xilinx Kintex-7) using Xilinx Vivado for synthesis.

Description

Your task is to port PULPissimo to the Digilent ZedBoard FPGA+SoC development board (featuring a Zynq 7020 FPGA+ARM SoC).
This includes...
* refining the build process of PULPissimo to support the ZedBoard as synthesis target,
* providing the necessary glue logic between the ARM SoC in the FPGA and the configurable logic hosting the soft-core RISC-V CPU,
* modifying the SDK and similar infrastructure software (e.g., debugging bridge) to use the glue logic above to communicate with RISC-V CPU.
Many of the required parts can be based on the counterparts found in the PULPino implementation for the ZedBoard. The minimum outcome of the project shall be a demo application running on PULPissimo within the configurable logic of the ZedBoard that can be debugged from the ARM core.

Required Skills

Experience with Xilinx Vivado, (System)Verilog, system programming (in C/C++ ), TCL scripts, CMake (in order of usefulness) are advantageous but no necessity.

Supervisors

Dipl.-Ing. Dr.techn. Andreas STEININGER (main responsibility)
E-Mail:
Homepage: https://ti.tuwien.ac.at/ecs/people/steininger/view

Types

Praktikum

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