Practicals & Theses

List of practicals and theses at the institute (see also TI Research Presentations)

Details for TTNoC boundary test with interleaved messages (New, exciting, and promising!)

Masterarbeit ::: Seminar mit Bachelorarbeit + Projektpraktikum ::: Building on the Unique Selling Proposition of time-triggered systems, the predictability, interleave test messages with regular traffic to iteratively identify and ultimately pinpoint faulty network links.


The Time-Triggered System-on-Chip Architecture (TTSoCA) brings the successful time-triggered paradigm to multi-processor cores, which emerge due to the diminishing returns from uniprocessor optimizations. The time-triggered paradigm is realized in the TTP/C protocol (e.g., deployed in the Airbus A380) and TTEthernet (e.g., deployed in the NASA Orion crew vehicle/spaceship). The time-triggered communication entails the feasible temporal prediction of the traffic in the Time-Triggered Network-on-Chip (TTNoC). The predictability is the Unique Selling Proposition of our TTSoCA architecture. Based on this predictability we envision a TTNoC boundary test with test messages interleaved in the regular traffic. We inject test messages in free communication slots in order to test network routes. Iteratively, faulty subroutes or even single faulty lanes are isolated and reconfiguration & recovery mechanisms applied (e.g., rerouting). The aim of this work is implement this idea to demonstrate feasibility. Finally, we subject this TTNoC boundary test to fault injection in order to proof high error detection coverage. As a reference for what is going on in the field of NoC diagnosis have a look at the following workshop digest.


Dipl.-Ing. Harald PAULITSCH (main responsibility)


Praktikum, Seminar, Diplomarbeit