Publications

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Presentations

M. Schoeberl, B. Cilku, D. Prokesch, P. Puschner: Best Practice for Caching of Single-Path Code
17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017), Dubrovnik, Croatia; in: Proc. 17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017), Dagstuhl, Germany (2017), ISBN: 978-3-95977-057-6, p. 1 - 12
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B. Cilku, W. Puffitsch, D. Prokesch, M. Schoeberl, P. Puschner: Improving Performance of Single-path Code Through a Time-predictable Memory Hierarchy
20th IEEE International Symposium on Real-Time Computing (ISORC 2017), Toronto, Canada; in: Proc. 20th IEEE International Symposium on Real-Time Computing (ISORC 2017), IEEE, 2017, ISBN: 978-1-5386-1574-4, p. 76 - 83
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J. Träff (invited): High Performance Expectations for MPI
Friedrich-Alexander-Universität Erlangen-Nürnberg, Prof. Dr. Gerhard Wellein, Erlangen, Germany
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M. Jung, J. Park, J. Blieberger, B. Burgstaller: Parallel Construction of Simultaneous Deterministic Finite Automata on Shared-memory Multicores
International Conference on Parallel Processing, Bristol; in: Proceedings of the 46th International Conference on Parallel Processing (ICPP-2017), IEEE, 2017, ISSN: 2332-5690, p. 271 - 281
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E. Wimmer: Is Gossip-inspired reduction competitive in high performance computing?
International Workshop on Parallel Numerics (PARNUM 2017), Waischenfeld, Germany
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W. Sodsong, R. Mittermayr, Y. Park, B. Burgstaller, J. Blieberger: Lazy Parallel Kronecker Algebra-Operations on Heterogeneous Multicores
Euro-Par 2017 23rd International European Conference on Parallel and Distributed Computing, Santiago de Compostela, Spain; in: Proceedings of the 23rd International European Conference on Parallel and Distributed Computing (Euro-Par 2017), LNCS / Springer Verlag, 10417 / Santiago de Compostela, Spain (2017), ISBN: 978-3-319-64202-4, p. 538 - 552
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J. Träff (invited): High Performance Expectations for MPI
Austrian HPC Meeting 2017 - AHPC 2017, Grundlsee, Austria; in: AHPC 2017, Austrian HPC Meeting 2017, G. Baumgartner, J. Courian (ed.); FSP Scientific Computing, University of Innsbruck, 2017, p. 33
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M. Meisel, S. Wilker, M. Kammerstetter, M. Müllner, D. Fasthuber, W. Kastner, W. Gawlik (invited): Reference Architecture as Foundation for Risk and Threat Analysis
Symposium On Innovative Smart Grid Cybersecurity Solutions, Wien; in: http://smartgrid-cybersecurity.events/call-for-posters/, Facultas, Wien (2017); 1 pages
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I. Konnov, J. Widder, F. Spegni, L. Spalazzi: Accuracy of Message Counting Abstraction in Fault-Tolerant Distributed Algorithms
Verification, Model Checking, and Abstract Interpretation (VMCAI), Paris; in: VMCAI 2017: Verification, Model Checking, and Abstract Interpretation, Springer, LNCS/10145/Paris (2017), ISBN: 978-3-319-52233-3, p. 347 - 366
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I. Konnov, M. Lazić, H. Veith, J. Widder: A short counterexample property for safety and liveness verification of fault-tolerant distributed algorithms
44th ACM SIGPLAN Symposium on Principles of Programming Languages (POPL), Paris, France; in: POPL, ACM, Paris (2017), ISBN: 978-1-4503-4660-3, p. 719 - 734
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A. Dabrowski, G. Petzl, E. Weippl: The Messenger Shoots Back: Network Operator Based IMSI Catcher Detection
19th International Symposium on Research in Attacks, Intrusions and Defenses (RAID 2016), Paris, France; in: RAID 2016: Research in Attacks, Intrusions, and Defenses, Lecture Notes in Computer Science, 9854 (2016), p. 279 - 302
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T. Frühwirth, I. Ayatollahi, F. Pauker, W. Kastner, B. Kittl, T. Trautner, G. Gridling, C. Kudera, M. Kammerstetter: DigiTrans Modul3 - Praxistag 4: Security
DigiTrans 4.0 - Innovationslehrgang im Themenfeld Industrie 4.0, Wien
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T. Frühwirth, I. Ayatollahi, F. Pauker, W. Kastner, B. Kittl, T. Trautner, G. Gridling: DigiTrans Modul3 - Praxistag 3: OPC Unified Architecture
DigiTrans 4.0 - Innovationslehrgang im Themenfeld Industrie 4.0, Wien
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T. Frühwirth, I. Ayatollahi, F. Pauker, W. Kastner, B. Kittl, T. Trautner, G. Gridling: DigiTrans Modul3 - Praxistag 2: Automatisierungstechnik und automatisierte Fertigungssysteme
DigiTrans 4.0 - Innovationslehrgang im Themenfeld Industrie 4.0, Wien
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T. Frühwirth, I. Ayatollahi, F. Pauker, W. Kastner, B. Kittl, T. Trautner, G. Gridling: DigiTrans Modul3 - Praxistag 1: Integration
DigiTrans 4.0 - Innovationslehrgang im Themenfeld Industrie 4.0, Wien
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M. Meisel, S. Wilker, J. Fabini, R. Annessi, T. Zseby, M. Müllner, W. Kastner, M. Litzlbauer, W. Gawlik, C. Neureiter (invited): Methodical Reference Architecture Development Progress
D-A-CH Energieinformatik Konferenz, Klagenfurt
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A. Kinali, F. Huemer, C. Lenzen: Fault-tolerant Clock Synchronization with High Precision
2016 IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, USA; in: Proc. 2016 IEEE Computer Society Annual Symposium on VLSI, 2016, p. 490 - 495
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T. Polzer, A. Steininger: A General Approach for Comparing Metastable Behavior of Digital CMOS Gates
19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Kosice, Slovakia; in: Proc 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2016, ISBN: 978-1-5090-2467-4; 6 pages
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V. S. Veeravalli, A. Steininger: Study of a Delayed Single-Event Effect in the Muller C-element
21st IEEE European Test Symposium, Amsterdam; in: Proc 21st IEEE European Test Symposium, 2016, ISBN: 978-1-4673-9659-2
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V. S. Veeravalli, A. Steininger: Design and Physical Implementation of a Target ASIC for SET Experiments
2016 Euromicro Conference on Digital System Design (DSD), Limassol, Portugal; in: Proc. 2016 Euromicro Conference on Digital System Design (DSD), IEEE, 2016, ISBN: 978-1-5090-2817-7, p. 694 - 697
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