Publications

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Journal Papers

B. Charron-Bost, M Függer, T. Nowak: New transience bounds for max-plus linear systems
Discrete Applied Mathematics, 219 (2017), p. 83 - 99
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T. Polzer, A. Steininger: A Model for the Metastability Delay of Sequential Elements
Journal of Circuits, Systems, and Computers, 26 (2017), p. 174001001 - 174001022
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J. Qadir, A. Sathiaseelan, U. Farooq, M. Usama, M. Imran, M. Shafique: Approximate Networking for Universal Internet Access
Future Internet, 9 (2017), p. 1 - 23
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S. Mazahir, O. Hasan, R. Hafiz, M. Shafique: Probabilistic Error Analysis of Approximate Recursive Multipliers
IEEE Transactions on Computers, 66 (2017), p. 1982 - 1990
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A. Pathania, V. Venkataramani, M. Shafique, T. Mitra, J. Henkel: Optimal Greedy Algorithm for Many-Core Scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36 (2017), p. 1054 - 1058
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S. Pagani, A. Pathania, M. Shafique, J. Chen, J. Henkel: Energy Efficiency for Clustered Heterogeneous Multicores
IEEE Transactions on Parallel and Distributed Systems, 28 (2017), p. 1315 - 1330
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M. Shafique, S. Garg: Computing in the Dark Silicon Era: Current Trends and Research Challenges
Ieee Design & Test, 34 (2017), p. 8 - 23
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A. Pathania, V. Venkataramani, M. Shafique, T. Mitra, J. Henkel: Defragmentation of Tasks in Many-Core Architecture
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 14 (2017), p. 2:1 - 2:21
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T. Li, M. Shafique, J. Ambrose, J. Henkel, S. Parameswaran: Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors
IEEE Transactions on Computers, 66 (2017), p. 647 - 660
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M. Shafique, S. Rehman, F. Kriebel, M. Khan, B. Zatt, A. Subramaniyan, B. Vizzotto, J. Henkel: Application-Guided Power-Efficient Fault Tolerance for H.264 Context Adaptive Variable Length Coding
IEEE Transactions on Computers, 66 (2017), p. 560 - 574
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S. Mazahir, O. Hasan, R. Hafiz, M. Shafique, J. Henkel: Probabilistic Error Modeling for Approximate Adders
IEEE Transactions on Computers, 66 (2017), p. 515 - 530
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K. Khdr, S. Pagani, E. Sousa, V. Lari, A. Pathania, F. Hannig, M. Shafique, J. Teich, J. Henkel: Power Density-Aware Resource Management for Heterogeneous Tiled Multicores
IEEE Transactions on Computers, 66 (2017), p. 488 - 501
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S. Pagani, K. Khdr, J. Chen, M. Shafique, M. Li, J. Henkel: Thermal Safe Power (TSP): Efficient Power Budgeting for Heterogeneous Manycore Systems in Dark Silicon
IEEE Transactions on Computers, 66 (2017), p. 147 - 162
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S. Varadan, A. Steininger, U. Schmid: A versatile architecture for long-term monitoring of single-event transient durations
Microprocessors and Microsystems, 53 (2017), p. 130 - 144
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I. Konnov, M. Lazić, V. Veith, J. Widder (invited): Para^2: Parameterized Path Reduction, Acceleration, and SMT for Reachability in Threshold-Guarded Distributed Algorithms
Formal Methods in System Design, 51 (2017), p. 270 - 307
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T. Polzer, F. Huemer, A. Steininger: Refined Metastability Characterization Using a Time-to-Digital Converter
Microelectronics Reliability, 80 (2018), p. 91 - 99
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E. Bartocci, L. Bortolussi, T. Brazdil, D. Milos, G. Sanguinetti: Policy learning in Continuous-Time Markov Decision Processes using Gaussian Processes
Performance Evaluation, 116 (2017), p. 84 - 100
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I. Konnov, V. Veith, J. Widder: On the completeness of bounded model checking for threshold-based distributed algorithms: Reachability
Information and Computation, 252 (2017), p. 95 - 109
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M. Shafique, A. Ivanov, B. Vogel, J. Henkel: Scalable Power Management for On-Chip Systems with Malleable Applications
IEEE Transactions on Computers, 65 (2016), p. 3398 - 3412
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K. Chen, J. Chen, F. Kriebel, S. Rehman, M. Shafique, J. Henkel: Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity
IEEE Transactions on Computers, 65 (2016), p. 3441 - 3454
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M. Shafique, M. Usman Karim Khan, J. Henkel: Content-Aware Low-Power Configurable Aging Mitigation for SRAM Memories
IEEE Transactions on Computers, 65 (2016), p. 3617 - 3630
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M Függer, T. Nowak, U. Schmid: Unfaithful Glitch Propagation in Existing Binary Circuit Models
IEEE Transactions on Computers, 65 (2016), p. 964 - 978
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E. Bartocci, E. Aydin Gol, I. Haghighi, C. Belta: A Formal Methods Approach to Pattern Recognition and Synthesis in Reaction Diffusion Networks
IEEE Transactions on Control of Network Systems, PP (2016), p. 1 - 12
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L. Esterle, R. Grosu (invited): Cyber-physical systems: challenge of the 21st century
Elektrotechnik und Informationstechnik, 133 (2016), p. 299 - 303
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R. Bloem, S. Jacobs, A. Khalimov, I. Konnov, S. Rubin, V. Veith, J. Widder: Decidability of Parameterized Verification
ACM SIGACT News, 47 (2016), p. 53 - 64
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D. Dolev, M Függer, C. Lenzen, M. Perner, U. Schmid: HEX: Scaling Honeycombs is Easier than Scaling Clock Trees
Journal of Computer and System Sciences, 82 (2016), p. 929 - 956
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M. Schoeberl, S. Abbaspour, B. Akesson, N. Audsley, R. Capasso, J. Garside, K. Goossens, S. Goossens, S. Hansen, R. Heckmann, S Hepp, B. Huber, A. Jordan, E. Kasapaki, J. Knoop, Y. Li, D. Prokesch, W. Puffitsch, P. Puschner, A. Rocha, C Silva, J. Sparso, A. Tocchi: T-CREST: Time-Predictable Multi-Core Architecture for Embedded Systems
Journal of Systems Architecture, Volume 61 (2015), p. 449 - 471
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S. Resch, A. Steininger, C. Scherrer: A Composable Real-Time Architecture for Replicated Railway Applications
Journal of Systems Architecture, 61 (2015), p. 472 - 485
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T. Polzer, R. Najvirt, F. Beck, A. Steininger: On the Appropriate Handling of Metastable Voltages in FPGAs
Journal of Circuits, Systems, and Computers, 25 (2015), p. 1640020-1 - 1640020-25
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D. Dolev, M Függer, C. Lenzen, U. Schmid, A. Steininger: Fault-tolerant Distributed Systems in Hardware
Bulletin of the EATCS, 2 (2015)
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E. Bartocci, P. Lio: Computational modeling, formal analysis and tools for systems biology
PLoS Computational Biology, 12 (2016), p. 1 - 22
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B. Charron-Bost, M Függer, L. Welch, J. Widder: Time Complexity of Link Reversal Routing
ACM Transactions on Algorithms, 11 (2015), p. 1 - 39
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A. Steininger, H. Zimmermann, A. Jantsch, M. Hofbauer, U. Schmid, K. Schweiger, S. Varadan: Building reliable systems-on-chip in nanoscale technologies
E&I Elektrotechnik und Informationstechnik, 132 (2015), p. 301 - 306
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M Függer, A. Kößler, T. Nowak, U. Schmid, M. Zeiner: The effect of forgetting on the performance of a synchronizer
Performance Evaluation, 93 (2015), p. 1 - 16
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E. Bartocci et al.: Teaching cardiac electrophysiology modeling to undergraduate students: Laboratory exercises and GPU programming for the study of arrhythmias and spiral wave dynamics
Advances in Physiology Education, 35 (2011), p. 427 - 437
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R. Alfieri, E. Bartocci, E. Merelli, L. Milanesi: Modeling the cell cycle: From deterministic models to hybrid systems
Biosystems, 105 (2011), p. 34 - 40
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E. Bartocci, L. Bortolussi, L. Nenzi, G. Sanguinetti: System Design of Stochastic Models using Robustness of Temporal Properties
Theoretical Computer Science, 587 (2015), p. 3 - 25
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M. Biely, P. Robinson, U. Schmid: The Generalized Loneliness Detector and Weak System Models for k-Set Agreement
IEEE Transactions on Parallel and Distributed Systems, 25 (2014), p. 1078 - 1088
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H. Moser, U. Schmid: Reconciling fault-tolerant distributed algorithms and real-time computing
Distributed Computing, 27 (2014), p. 203 - 230
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D. Dolev, M Függer, U. Schmid, C. Lenzen: Fault-tolerant Algorithms for Tick-generation in Asynchronous Logic: Robust Pulse Generation
Journal of the ACM, 61 (2014), p. 1 - 74
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E. Bartocci, O. Höftberger, R. Grosu (invited): Cyber-Physical Systems: Theoretical and Practical Challenges
ERCIM NEWS, 2014 (2014), p. 8 - 9
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I. Ariful, A. Murthy, E. Bartocci, E. Cherry, F. Fenton, J. Glimm, S. Smolka, R. Grosu: Model-Order Reduction of Ion Channel Dynamics Using Approximate Bisimulation
Theoretical Computer Science, 599 (2015), p. 34 - 46
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M. Molnar, D. Donoval, J. Kuzmik, J. Marek, A. Chvala, P. Pribytny, V. Mikolasek, K. Rendek, V. Palankovski: Simulation Study of Interface Traps and Bulk Traps in n++GaN/InAlN/AlN/GaN High Electron Mobility Transistors
Applied Surface Science, 312 (2014), p. 157 - 161
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S. Kandl, S. Chandrashekar: Reasonability of MC/DC for Safety-Relevant Software Implemented in Programming Languages with Short-Circuit Evaluation
Computing, 607 (2014)
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T. Reinbacher, J. Brauer, M. Horauer, A. Steininger, S. Kowalewski: Runtime verification of microcontroller binary code
Science of Computer Programming, 80 (2014), p. 109 - 129
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B. Rahbaran, A. Steininger: Is Asynchronous Logic More Robust Than Synchronous Logic?
IEEE Transactions on Dependable and Secure Computing, 6 (2009), p. 282 - 294
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D. Dolev, M Függer, M. Posch, U. Schmid, A. Steininger, C. Lenzen: Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip
Journal of Computer and System Sciences, 80 (2014), p. 860 - 900
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M. Zeiner: On a family of $q$-binomial distributions
Mathematica Slovaca, 64 (2014), p. 479 - 510
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M. Hofbauer, K. Schweiger, H. Zimmermann, U. Giesen, F. Langner, U. Schmid, A. Steininger: Supply Voltage Dependent On-Chip Single-Event Transient Pulse Shape Measurements in 90-nm Bulk CMOS Under Alpha Irradiation
IEEE Transactions on Nuclear Science, 60 (2013), p. 2640 - 2646
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S. Varadan, T. Polzer, U. Schmid, A. Steininger, M. Hofbauer, K. Schweiger, H. Dietrich, K. Schneider-Hornstein, H. Zimmermann, K. Voss, B. Merk, M. Hajek: An infrastructure for accurate characterization of single-event transients in digital circuits
Microprocessors and Microsystems, 37 (2013), p. 772 - 791
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T. Nowak, M Függer, A. Kößler: On the performance of a retransmission-based synchronizer
Theoretical Computer Science, 509 (2013), p. 25 - 39
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T. Reinbacher, M Függer, J. Brauer: Runtime verification of embedded real-time systems
Formal Methods in System Design, Nov 2013 (2013), p. 1 - 37
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C. El Salloum, M. Elshuber, O. Höftberger, H. Isakovic, A. Wasicek: The ACROSS MPSoC - A new generation of multi-core processors designed for safety-critical embedded systems
Microprocessors and Microsystems, 37 (2013), p. 1020 - 1032
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M. Elshuber, R. Obermaisser: Dependable and predictable time-triggered Ethernet networks with COTS components
Journal of Systems Architecture, Volume 59, Issue 9 (2013), p. 667 - 690
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J. Seyster, K. Dixit, X. Huang, R. Grosu, K Havelund, S. Smolka, S. Stoller, E. Zadok: InterAspect: aspect-oriented instrumentation with GCC
Formal Methods in System Design, 41 (2012), p. 295 - 320
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M Függer, U. Schmid: Reconciling fault-tolerant distributed computing and systems-on-chip
Distributed Computing, 24 (2012), p. 323 - 355
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M. Hofbauer, K. Schweiger, H. Dietrich, H. Zimmermann, K.O. Voss, B Merk, U. Schmid, A. Steininger: Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating Through a 90 nm Bulk CMOS Inverter Chain
IEEE Transactions on Nuclear Science, vol 59 (2012), p. 2778 - 2784
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A. Murthy, E. Bartocci, F. Fenton, J. Glimm, R. Gray, E. Cherry, S. Smolka, R. Grosu: Curvature Analysis of Cardiac Excitation Wavefronts
IEEE/ACM Transactions on Computational Biology and Bioinformatics, 10 (2013), p. 323 - 336
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M. Schoeberl, B. Huber, W. Puffitsch: Data cache organization for accurate timing analysis
Real-Time Systems, 49 (2013), p. 1 - 28
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R. Kammerer, R. Obermaisser, B. Frömel: A router for the containment of timing and value failures in CAN
EURASIP Journal on Embedded Systems, 2012 (2012)
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X. Huang, J. Seyster, S. Callanan, K. Dixit, R. Grosu, S. Smolka, S. Stoller, E. Zadok: Software monitoring with controllable overhead
International Journal on Software Tools for Technology Transfer, 14 (2012), p. 327 - 347
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E. Bartocci, D. Cacciagrano, M. Di Berardini, E. Merelli, L. Vito: UBioLab: a web-LABoratory for Ubiquitous in-silico experiments
Journal of Integrative Bioinformatics, 9 (2012), p. 1 - 20
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E. Bartocci, P. Lio, E. Merelli, N. Paoletti: Multiple Verification in Complex Biological Systems: The Bone Remodelling Case Study
Transactions on Computational Systems Biology, XIV (2012), p. 53 - 76
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B. Huber, W. Puffitsch, M. Schoeberl: Worst-case execution time analysis-driven object cache design
Concurrency and Computation: Practice and Experience, Volume 24 Issue 8 (2012), p. 753 - 771
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J. Widder, M. Biely, G. Gridling, B. Weiss, J. Blanquart: Consensus in the presence of mortal Byzantine faulty processes
Distributed Computing, 24 (2012), p. 299 - 321
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P. Robinson, U. Schmid: The Asynchronous Bounded-Cycle Model
Theoretical Computer Science, 412 (2011), p. 5580 - 5601
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M. Biely, U. Schmid, B. Weiss: Synchronous consensus under hybrid process and link failures
Theoretical Computer Science, 412 (2011), p. 5602 - 5630
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A. Steininger, G. Fuchs: VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation
Journal of Electrical and Computer Engineering, Clock/Frequency Generation Circuits and Systems (2011), p. 23
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A. Steininger, P Tummeltshammer: Replicated processors on a single die - How independently do they fail?
Journal e&i: Elektrotechnik und Informationstechnik, 128 (2011), p. 245 - 250
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M. Ferringer: On Self-Timed Circuits in Real-Time Systems
International Journal of Reconfigurable Computing, 2011 (2011)
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B. Thallner, H. Moser, U. Schmid: Topology Control for Fault-Tolerant Communication in Wireless Ad Hoc Networks
Wireless Networks, 16 (2010), p. 388 - 404
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B. Charron-Bost, M. Hutle, J. Widder: In search of lost time
Information Processing Letters, 110 (2010), p. 928 - 933
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C. Pitter, M. Schoeberl: A real-time Java chip-multiprocessor
ACM Transactions on Embedded Computing Systems, 10 (2010), p. 1 - 34
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R. Kirner, P. Puschner, A. Prantl: Transforming Flow Information during Code Optimization for Timing Analysis
Real-Time Systems, 45 (2010), p. 72 - 105
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M. Schoeberl: Scheduling of Hard Real-Time Garbage Collection
Real-Time Systems, 45 (2010), p. 176 - 213
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M. Schoeberl, W. Puffitsch, R. Pedersen, B. Huber: Worst-case execution time analysis for a Java processor
Software: Practice and Experience, 40 (2010), p. 507 - 542
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R. Kirner, J. Knoop, A. Prantl, M Schordan, A. Kadlec: Beyond Loop Bounds: Comparing Annotation Languages for Worst-Case Time Analysis
Journal of Software and Systems Modeling (online-edition), oB (2010)
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R. Obermaisser, H. Kopetz, S. Kuster: GENESYS (GENeric Embedded SYStem) - A Candidate for an ARTEMIS Cross-Domain Reference Architecture for Embedded Systems
ARTEMIS Magazine, 5 (2009), p. 32 - 34
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U. Schmid, B. Weiss, I. Keidar: Impossibility Results and Lower Bounds For Consensus Under Link Failures
SIAM JOURNAL ON COMPUTING, 38 (2009), p. 1912 - 1951
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M. Hutle, D. Malkhi, U. Schmid, L. Zhou: Chasing the Weakest System Model for Implementing Omega and Consensus
IEEE Transactions on Dependable and Secure Computing, 6 (2009), p. 269 - 279
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M Függer, A. Steininger, E. Armengaud: Safely Stimulating the Clock Synchronization Algorithm in Time-Triggered Systems - A Combined Formal and Experimental Approach
IEEE Transactions on Industrial Informatics, 5 (2009), p. 132 - 145
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H. Moser: Towards a real-time distribiuted computing model
Theoretical Computer Science, 410 (2008), p. 631 - 659
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J. Widder, M. Biely: Optimal Message-Driven Implementations of Omega with Mute Processes
ACM Transactions on Autonomous and Adaptive Systems., 4 (2009), p. ?
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J. Widder, U. Schmid: The Theta-Model: achieving synchrony without clocks
Distributed Computing, 22 (2009), p. 29 - 47
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S. Tauböck, P. Jahn, T. Polzer, A. Schuster: An Object-oriented DEV Approach to ARGESIM Benchmark C16 `Restaurant Business Dynamics´ using Enterprise Dynamics
Simulation News Europe SNE, 18 (2008), p. 41 - 42
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V. Legourski, Y. Huang, O. Cevan, F. Breitenecker: Statechart Modelling for ARGESIM Benchmark C10 `Dining Philosophers Problem II´ using Simulink/Stateflow
Simulation News Europe SNE, 18 (2008), p. 39 - 40
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M. Gyimesi, A. Dielacher, T. Handl, C. Wittmann: An Object-oriented Solution to ARGESIM Benchmark C4 `Dining Philosophers Problem´ implemented with AnyLogic
Simulation News Europe SNE, 18 (2008), p. 31 - 32
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R. Kirner, S. Kandl: Test Coverage Analysis and Preservation for Requirements-Based Testing of Safety-Critical Systems
ERCIM NEWS, 75 (2008), p. 40 - 41
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E. Armengaud, A. Steininger, M. Horauer: Towards a Systematic Test for Embedded Automotive Communication Systems
IEEE Transactions on Industrial Informatics, 4 (2008), p. 145 - 208
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M. Schoeberl: A Java processor architecture for embedded real-time systems
Journal of Systems Architecture, Volume 54, Issues 1-2 (2008), p. 265 - 286
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U. Schmid, A. Steininger, M. Sust: FIT-IT Projekt DARTS: Dezentrale fehlertolerante Taktgenerierung
Elektrotechnik und Informationstechnik (e&i), Heft 1-2 (2007), p. 3 - 8
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W. Steiner: Advancements in Dependable Time-Triggered Communication
Lecture Notes in Computer Science, 4761 (2007), p. 57 - 66
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M. Schlager, R. Obermaisser, W. Elmenreich: A Framework for Hardware-in-the-Loop Testing of an Integrated Architecture
Lecture Notes in Computer Science, 4761 (2007), p. 159 - 170
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M. Schoeberl: Mission Modes for Safety Critical Java
Lecture Notes in Computer Science, 4761 (2007), p. 105 - 113
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W. Elmenreich: A Review on System Architectures for Sensor Fusion Applications
Lecture Notes in Computer Science, 4761 (2007), p. 547 - 559
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W. Elmenreich: Fusion of Continuous-valued Sensor Measurements using Confidence-weighted Averaging
Journal of Vibration and Control, 13 (2007), p. 1303 - 1312
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I. Wenzel, R. Kirner, B. Rieder, P. Puschner: Cross-Platform Verification Framework for Embedded Systems
Lecture Notes in Computer Science, 4761 (2007), p. 137 - 148
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A. Hanzlik: SIDERA - a Simulation Model for Time-Triggered Distributed Systems
International Review on Computers and Software (IRECOS), 1 (2006), p. 181 - 193
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A. Hanzlik: Stability and Performance Analysis of Clock Synchronization in FlexRay
International Review on Computers and Software (IRECOS), 1 (2006), p. 146 - 155
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W. Herzner, B. Huber, C. György, A. Balogh: The DECOS Tool-Chain: Model-Based Development of Distributed Embedded Safety-Critical Real-Time Systems
ERCIM NEWS, 67 (2006), p. 22 - 24
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R. Obermaisser, P. Peti, B. Huber, C. El Salloum: DECOS: An Integrated Time-Triggered Architecture
Journal e&i: Elektrotechnik und Informationstechnik, 3 (2006), p. 83 - 95
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D. Albeseder, M Függer, F. Breitenecker, T. Löscher, S. Tauböck: Small PC-Network Simulation -- A Comprehensive Performance Case Study
Simulation News Europe, 44/45 (2005), p. 26 - 32
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H. Kopetz, A. Ademaj, A. Hanzlik: Combination of clock-state and clock-rate correction in fault-tolerant distributed systems
Real-Time Systems, 33 (2006), p. 139 - 173
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W. Steiner, M. Paulitsch, H. Kopetz: The TTA's Approach to Resilience after Transient Upsets
Real-Time Systems, 32 (2006), p. 213 - 233
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W. Elmenreich: Time-Triggered Smart Transducer Networks
IEEE Transactions on Industrial Informatics, 2 (2006), p. 192 - 199
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W. Elmenreich, W. Haidinger, H. Kopetz, T. Losert, R. Obermaisser, H. Paulitsch, P. Peti: A Standard for Real-time Smart Transducer Interface
Computer Standards & Interfaces, 28 (2006), p. 613 - 624
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T. Losert, M. Schlager, W. Elmenreich: Fault-Tolerant Compensation of the Propagation Delay for Hard Real-Time Systems
Journal of Advanced Computational Intelligence and Intelligent Informatics, 9 (2005), p. 346 - 352
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M. Delvai, U. Eisenmann, W. Elmenreich: A Generic Architecture for Integrated Smart Transducers
Lecture Notes in Computer Science, 2778 (2003), p. 733 - 744
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A. N. Rapaka, W. Elmenreich, D. Wunsch: TTP/A Protocol and Design
Circuit Cellar, 2004, p. 12 - 21
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H. Kopetz, R. Obermaisser, U. Schmid (invited): Dependable Embedded Systems Research at TU Vienna
Elektrotechnik und Informationstechnik (e&i), 1 (2005), p. 33 - 37
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B. Rahbaran, M Függer, A. Steininger: Embedded Real-Time-Tracer -- An Approach with IDE
Telematik, 3-4 (2004), p. 16 - 20
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B. Huber, W. Elmenreich: Wireless Time-Triggered Real-Time Communication
Telematik, 3-4 (2004), p. 44 - 50
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M. Jakovljevic, M. Schlager, M. Plankensteiner, S. Poledna: Safety Relevant Automotive Electronic Solutions
Automotive Electronics International, March (2004), p. 21 - 23
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M. Jakovljevic, M. Schlager, M. Plankensteiner, S. Poledna: Sicherheitsrelevante elektronische Lösungen im Automobil
Automotive Elektronics, extra (2004), p. 50 - 53
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C. Scherrer, A. Steininger: Dealing With Dormant Faults in an Embedded Fault-Tolerant Computer System
IEEE Transactions on Reliability, 52 (2003), p. 512 - 522
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K. Thaller, A. Steininger: A Transparent Online Memory Test for Simultaneous Detection of Functional Faults and Soft Errors in Memories
IEEE Transactions on Reliability, 52 (2003), p. 413 - 422
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U. Schmid, K. Schossmaier: Interval-based clock synchronization with optimal precision.
Information and Computation, 186 (2003), p. 36 - 77
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H. Kopetz: Time Triggered Architecture
ERCIM NEWS, 1 (2003), p. 24 - 25
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H. Kopetz, G. Bauer: The Time-Triggered Architecture
Proceedings of the IEEE, 91 (2003), p. 112 - 126
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S. Poledna, P. Barrett, A. Burns, A. Wellings: Replica Determinism and Flexible Scheduling in Hard Real-Time Dependable Systems
IEEE Transactions on Computers, 49 (2000), p. 100 - 111
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P. Puschner, A. Burns: A Review of Worst-Case Execution-Time Analysis
Real-Time Systems, 18 (2000), p. 115 - 128
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W. Elmenreich: Kostengünstig vernetzen mit TTP/A
Markt & Technik, 38 (2000), p. 42 - 44
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H. Kopetz, R. Obermaisser (invited): Temporal Composability
IEE's Computing & Control Engineering Journal, 13 (2002), p. 156 - 162
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R. Maier, G. Bauer, G. Stöger, S. Poledna: Time-Triggered Architecture: A Consistent Computing Platform
IEEE Micro, 22 (2002), p. 36 - 45
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D. Maurer, V. Salapura, M. Gschwind: FPGA prototyping of a RISC processor core for embedded applications
IEEE Transactions on Computers, 9 (2001), p. 241 - 250
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A. Steininger, C. Scherrer: Identifying Efficient Combinations of Error Detection Mechanisms Based on Results of Fault-Injection Experiments
IEEE Transactions on Computers, 51 (2002), p. 235 - 239
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A. Steininger, C. Scherrer: Vom Lenkrad zum Joystick
Elektrotechnik und Informationstechnik (e&i), 11 (2000), p. 714 - 720
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A. Steininger: Testing and Built-in-Self-Test - A Survey
Journal of Systems Architecture, 46 (2000), p. 721 - 747
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H. Kopetz, M. Holzmann, W. Elmenreich: A Universal Smart Transducer Interface: TTP/A
International Journal of Computer System, Science & Engineering, 16 (2001), p. 71 - 77
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