Practicals & Theses

List of practicals and theses at the Embedded Computing Systems Group (E191/2)

Implementation of delay-encoded spiking neural network links

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, 07. 03. 2023

Delay encoding is a power-efficient alternative to frequency encoding for implementing spiking neural network links, which are needed for communicating analog values between neurons. The goal of this assignment is to come up with a light-weight asynchronous implementation of such a link, and its experimental evaluation using digital and analog simulations.

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Gate Delay Characterization

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, 08. 08. 2019

Estimating the delay of a gate is a crucial task in digital circuit design. Whereas it is relatively easy to measure characteristic gate delay values like worst-case rising and falling transition delays via simulations, the question of determining these values for all the gates in a circuit without individual measurements. After all, both the surroundings of a gate (like load capacitance and interconnect characteristics) and operating conditions (like supply voltage and input slewrate) have a severe impact on gate delays. Models like CCSM and ECSM used in static timing analysis do a very good job for determining worst-case delays, but cannot provide all characteristic delay values of interest. The goal of this assignment is to explore ways to accomplish this.

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Experimental measurement of Schmitt Trigger Metastability

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 05. 07. 2019

Rather than assuming a stable HI or LO, digital storage elements can, under adverse conditions, also assume a so-called metastable state for some time. This undefined state creates problems in the subsequent logic. Quite unexpectedly, Schmitt Trigger circuits can also become metastable, even though their purpose is not data storage.

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Modelling of a Multistage Synchronizer

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 05. 07. 2019

At clock domain boundaries violation of setup- and hold time cannot be avoided. Synchronizers are used to mitigate the metastability that results from these violations. In modern technologies with their parameter variations and narrow timing margins, conventional single stage synchronizers are no more sufficient and need to be cascaded, thus forming multi-stage synchronizers. While theory provides a reasonably good estimation for the reliability (in terms of mean time between upsets, MTBU) of the single stage synchronizer, the MTBU estimation for the multi-stage synchronizer seems to be to simplistic. In particular, the influence of the input thresholds is currently not considered.

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Increasing Resilience of Schmitt Triggers against Metastability

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 05. 07. 2019

Schmitt Triggers, often used to block metastable voltages, can be driven into
metastability themselves. In detail it is possible to hold any voltage value between
ground and the supply voltage value at the output for an arbitrary amount of
time. To achieve these values gets however harder the faster the Schmitt Trigger
can operate, i.e., the higher the output derivatives gets. Of course this could
be achieved by scaling everything which is however not very beneficial. It is
therefore crucial to know which part of which component has a high impact on the
slope and just tune that parameter.

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Assigned Practicals

4 vs 2 phase Logic Design

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 05. 07. 2019

A general rule of thumb in asynchronous circuit design says that the 4-phase protocol is used for computation while the 2-phase one is used for communication. The reason is that 4-phase gates are smaller in size while the 2-phase protocol allows higher speed. The question that has however not yet been answered is the actual amount of the deviation. How much bigger are 2-phase gates compared to 4-phase? How much faster are they? This thesis therefore focuses on comparing different 2- and 4-phase implementations analytically and on an FPGA. Based on the achieved results the design of novel and innovative gates might become possible.

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Automatic Verification Framework of VHDL Code examples

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 05. 07. 2019

In the lecture Hardware Modeling training examples are provided via TUWEL
however it is not possible for the students to check if their solution is
working correctly. Therefore a framework is desired that accepts a piece of
code, runs test benches and reports the result back to the user. The used
procedure thereby has to satisfy the DSGVO and a certain level of security.

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Efficient Interfacing Between Timing Domains

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Bakk.techn. Robert NAJVIRT, Dipl.-Ing. Dr.techn. Thomas POLZER, 03. 10. 2012

Within a closed timing domain the setup/hold requirements of all stateful elements can be safely met. Examples are a globally synchronous clock domain or an asynchronous handshake domain. Often it is, however, necessary to exchange signals between two (or more) such timing domains, which inevidently leads to metastability problems at the interfaces.
Your task will be to compile and compare existing solutions for this problem (assumptions, overheads, throughput, upset rate,...), using analytic models and analog simulations. The whole matrix of interfaces between synchronous systems, bounded delay systems and delay insensitive systems shall be covered, considering the diverse levels of synchrony (mesochronous, plesiochronous) and the asynchropnous handshake protocols (2-phase, 4-phase). Where required, new solutions shall be developed, and existing ones be improved. Applicable tools for the proof of concept as well as the assessment of the solutions' properties are simulation and FPGA prototype implementation.

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