Practicals & Theses

List of practicals and theses at the Embedded Computing Systems Group (E191/2)

Predicting Analog Waveforms based on Digital Delay Estimation Schemes

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 08. 08. 2019

Simulating digital circuits at the analog level is a challenging and time-consuming task. To reduce simulation times, abstractions (primarily digital ones) are used that produce reasonably accurate results in a far less amount of time. The purpose of this assignment is the implementation of an analog abstraction and its experimental evaluation: Based on an existing digital delay estimation tool, which predicts when the analog waveform of a circuit hits a specific threshold voltage value, the analog waveform shall be approximated and compared to accurate analog simulations.

details

Approximating Analog Waveforms by adding Arbitrary Functions

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 08. 08. 2019

Tracing the analog behavior of a digital circuit is a very challenging task
and thus also very time consuming. To reduce simulation time, abstractions are
introduced that yield only slightly less accuracy in far less amount of
time. One example is to use rising and falling transitions of a certain function
family, e.g. sigmoids, and create pulses by properly adding these. It has
already been shown that this approach works well, however, until now no
qualified matching between input and output pulses could be established that
would enable a very simple and accurate analog estimation suite.

details

Gate Parameter Impact on Delay and its Prediction

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 08. 08. 2019

Estimating the delay of a gate is a crucial task in digital circuit design. 
While the actual simulation is easy and quickly done, characterization still
consumes a lot of time and effort: Each gate has to be matched
separately, as the surroundings, which play an important role, differ almost
certainly between various gates of the same type. The goal of this assignment
is to experimentally determine the impact of certain parameters on the delay
and to come up with an appropriate prediction model.

details

Loosening Bounds for Nondeterministic Delay Estimation

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 08. 08. 2019

Estimating the delay of a gate is a very crucial task in circuit
design. However, no matter how accurate the gate characterization is,
real circuits will always experience some manufacturing variations
and operating condition dependencies that lead to unpredictable
delay variations. We therefore augmented our novel involution delay
model by adding non-deterministic delay noise. Unfortunately, tight
bounds on the maximum variation had to be introduced in order to
retain the correctness properties of the model. The purpose of this
assignment is to relax these tight bounds, by exploiting the fact
that the delay noise primarily affects very short pulses in the
signal traces only.

details

Experimental measurement of Schmitt Trigger Metastability

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 05. 07. 2019

Rather than assuming a stable HI or LO, digital storage elements can, under adverse conditions, also assume a so-called metastable state for some time. This undefined state creates problems in the subsequent logic. Quite unexpectedly, Schmitt Trigger circuits can also become metastable, even though their purpose is not data storage.

details

Modelling of a Multistage Synchronizer

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 05. 07. 2019

At clock domain boundaries violation of setup- and hold time cannot be avoided. Synchronizers are used to mitigate the metastability that results from these violations. In modern technologies with their parameter variations and narrow timing margins, conventional single stage synchronizers are no more sufficient and need to be cascaded, thus forming multi-stage synchronizers. While theory provides a reasonably good estimation for the reliability (in terms of mean time between upsets, MTBU) of the single stage synchronizer, the MTBU estimation for the multi-stage synchronizer seems to be to simplistic. In particular, the influence of the input thresholds is currently not considered.

details

Porting of a RISC-V soft-core SoC (PULPissimo) to another FPGA platform

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 05. 07. 2019

PULPissimo is the improved successor of PULPino, which is an open-source SoC platform implementing a RISC-V-based microcontroller.
This family of processors was developed by the ETH Zürich and the University of Bologna as part of the PULP project: https://pulp-platform.org
The main focus of PULPissimo's development so far was on simulation and ASIC implementations. However, there also exists an implementation of PULPissimo for a Digilent Genesys 2 FPGA development board (hosting a Xilinx Kintex-7) using Xilinx Vivado for synthesis.

details

Increasing Resilience of Schmitt Triggers against Metastability

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 05. 07. 2019

Schmitt Triggers, often used to block metastable voltages, can be driven into
metastability themselves. In detail it is possible to hold any voltage value between
ground and the supply voltage value at the output for an arbitrary amount of
time. To achieve these values gets however harder the faster the Schmitt Trigger
can operate, i.e., the higher the output derivatives gets. Of course this could
be achieved by scaling everything which is however not very beneficial. It is
therefore crucial to know which part of which component has a high impact on the
slope and just tune that parameter.

details

Implementation of Pointer Authentication on a 32-bit RISC-V CPU

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 05. 07. 2019

Pointer Authentication (PA) is a method to strengthen the resilience of computer systems against attacks exploiting memory corruption.
If an attacker is able to redirect pointers she might gain control about the execution flow eventually.
Pointer Authentication is able to detect such modifications from unauthorized places in the code and thus thwart the malign consequences.
Industry has taken up this idea already from academia and is adding support to new implementations of existing microarchitectures (e.g., on ARMv8.3).

details

Assigned Practicals

Predicting Analog Waveforms based on Digital Delay Estimation Schemes

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 08. 08. 2019

Simulating digital circuits at the analog level is a challenging and time-consuming task. To reduce simulation times, abstractions (primarily digital ones) are used that produce reasonably accurate results in a far less amount of time. The purpose of this assignment is the implementation of an analog abstraction and its experimental evaluation: Based on an existing digital delay estimation tool, which predicts when the analog waveform of a circuit hits a specific threshold voltage value, the analog waveform shall be approximated and compared to accurate analog simulations.

details

Approximating Analog Waveforms by adding Arbitrary Functions

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 08. 08. 2019

Tracing the analog behavior of a digital circuit is a very challenging task
and thus also very time consuming. To reduce simulation time, abstractions are
introduced that yield only slightly less accuracy in far less amount of
time. One example is to use rising and falling transitions of a certain function
family, e.g. sigmoids, and create pulses by properly adding these. It has
already been shown that this approach works well, however, until now no
qualified matching between input and output pulses could be established that
would enable a very simple and accurate analog estimation suite.

details

Gate Parameter Impact on Delay and its Prediction

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 08. 08. 2019

Estimating the delay of a gate is a crucial task in digital circuit design. 
While the actual simulation is easy and quickly done, characterization still
consumes a lot of time and effort: Each gate has to be matched
separately, as the surroundings, which play an important role, differ almost
certainly between various gates of the same type. The goal of this assignment
is to experimentally determine the impact of certain parameters on the delay
and to come up with an appropriate prediction model.

details

Loosening Bounds for Nondeterministic Delay Estimation

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 08. 08. 2019

Estimating the delay of a gate is a very crucial task in circuit
design. However, no matter how accurate the gate characterization is,
real circuits will always experience some manufacturing variations
and operating condition dependencies that lead to unpredictable
delay variations. We therefore augmented our novel involution delay
model by adding non-deterministic delay noise. Unfortunately, tight
bounds on the maximum variation had to be introduced in order to
retain the correctness properties of the model. The purpose of this
assignment is to relax these tight bounds, by exploiting the fact
that the delay noise primarily affects very short pulses in the
signal traces only.

details

Experimental measurement of Schmitt Trigger Metastability

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 05. 07. 2019

Rather than assuming a stable HI or LO, digital storage elements can, under adverse conditions, also assume a so-called metastable state for some time. This undefined state creates problems in the subsequent logic. Quite unexpectedly, Schmitt Trigger circuits can also become metastable, even though their purpose is not data storage.

details

Modelling of a Multistage Synchronizer

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 05. 07. 2019

At clock domain boundaries violation of setup- and hold time cannot be avoided. Synchronizers are used to mitigate the metastability that results from these violations. In modern technologies with their parameter variations and narrow timing margins, conventional single stage synchronizers are no more sufficient and need to be cascaded, thus forming multi-stage synchronizers. While theory provides a reasonably good estimation for the reliability (in terms of mean time between upsets, MTBU) of the single stage synchronizer, the MTBU estimation for the multi-stage synchronizer seems to be to simplistic. In particular, the influence of the input thresholds is currently not considered.

details

Porting of a RISC-V soft-core SoC (PULPissimo) to another FPGA platform

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 05. 07. 2019

PULPissimo is the improved successor of PULPino, which is an open-source SoC platform implementing a RISC-V-based microcontroller.
This family of processors was developed by the ETH Zürich and the University of Bologna as part of the PULP project: https://pulp-platform.org
The main focus of PULPissimo's development so far was on simulation and ASIC implementations. However, there also exists an implementation of PULPissimo for a Digilent Genesys 2 FPGA development board (hosting a Xilinx Kintex-7) using Xilinx Vivado for synthesis.

details

Increasing Resilience of Schmitt Triggers against Metastability

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER, 05. 07. 2019

Schmitt Triggers, often used to block metastable voltages, can be driven into
metastability themselves. In detail it is possible to hold any voltage value between
ground and the supply voltage value at the output for an arbitrary amount of
time. To achieve these values gets however harder the faster the Schmitt Trigger
can operate, i.e., the higher the output derivatives gets. Of course this could
be achieved by scaling everything which is however not very beneficial. It is
therefore crucial to know which part of which component has a high impact on the
slope and just tune that parameter.

details

Implementation of Pointer Authentication on a 32-bit RISC-V CPU

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 05. 07. 2019

Pointer Authentication (PA) is a method to strengthen the resilience of computer systems against attacks exploiting memory corruption.
If an attacker is able to redirect pointers she might gain control about the execution flow eventually.
Pointer Authentication is able to detect such modifications from unauthorized places in the code and thus thwart the malign consequences.
Industry has taken up this idea already from academia and is adding support to new implementations of existing microarchitectures (e.g., on ARMv8.3).

details