Practicals & Theses

List of practicals and theses at the Embedded Computing Systems Group (E191/2)

Details for 4 vs 2 phase Logic Design

A general rule of thumb in asynchronous circuit design says that the 4-phase
protocol is used for computation while the 2-phase one is used for
communication. The reason is that 4-phase gates are smaller in size while the
2-phase protocol allows higher speed. The question that has however not yet been
answered is the actual amount of the deviation. How much bigger are 2-phase
gates compared to 4-phase? How much faster are they? This thesis therefore
focuses on comparing different 2- and 4-phase implementations analytically and
on an FPGA. Based on the achieved results the design of novel and innovative
gates might become possible.

Description

Your task is to search for suitable 4-phase and 2-phase logic gate designs,
implement them using a hardware description language (VHDL, Verilog) and
evaluate run time and area overhead analytically and by using simulations. If
possible novel implementations shall be developed which perform better in regard
to area/speed compared to the existing implementations.

Required Skills

VU Advanced Digital Design, Asynchronous Logic Design

Supervisors

Dipl.-Ing. Dr.techn. Andreas STEININGER
E-Mail:
Homepage: https://ti.tuwien.ac.at/ecs/people/steininger/view

Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER (main responsibility)
E-Mail:
Homepage: https://ti.tuwien.ac.at/ecs/people/jmaier

Types

Praktikum, Diplomarbeit

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