Practicals & Theses

List of practicals and theses at the Embedded Computing Systems Group (E191/2)

Details for Automatic Verification Framework of VHDL Code examples

In the lecture Hardware Modeling training examples are provided via TUWEL
however it is not possible for the students to check if their solution is
working correctly. Therefore a framework is desired that accepts a piece of
code, runs test benches and reports the result back to the user. The used
procedure thereby has to satisfy the DSGVO and a certain level of security.

Description

Your task will be to identify proper implementation methods for this
approach. Definitely there are several ways to realize such a framework. In the
following the test infrastructure and the single componets such as user
interface and communication, core functionality and simulation toolchain have to
be set up appropriately. For this framework it is very important to obey all
privacy constraints defined by the DSGVO and also implement a basic level of
security, as there is always a risk when executing external code. In the sequel
benchmarks for some simple examples have to be developed and run to verify the
feasability of the approach.

Required Skills

LU Digital Design & Computer Architecture, VO Hardware Modeling

Supervisors

Dipl.-Ing. Dr.techn. Andreas STEININGER
E-Mail:
Homepage: https://ti.tuwien.ac.at/ecs/people/steininger/view

Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc Jürgen MAIER (main responsibility)
E-Mail:
Homepage: https://ti.tuwien.ac.at/ecs/people/jmaier

Types

Praktikum, Diplomarbeit

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