Practicals & Theses

List of practicals and theses at the Embedded Computing Systems Group (E191/2)

Details for Modelling of a Multistage Synchronizer

At clock domain boundaries violation of setup- and hold time cannot be avoided. Synchronizers are used to mitigate the metastability that results from these violations. In modern technologies with their parameter variations and narrow timing margins, conventional single stage synchronizers are no more sufficient and need to be cascaded, thus forming multi-stage synchronizers. While theory provides a reasonably good estimation for the reliability (in terms of mean time between upsets, MTBU) of the single stage synchronizer, the MTBU estimation for the multi-stage synchronizer seems to be to simplistic. In particular, the influence of the input thresholds is currently not considered.

Description

Your task will be to study this influence in theory (circuit equations), simulation (SPICE) and, if possible, also experimentally. The outcome will be an improved model for the MTBU prediction of a multi-stage synchronizer that appropriately considers input thresholds.

Required Skills

VO Digital Design, LU Digitl design and Computer Architecture

Supervisors

Dipl.-Ing. Dr.techn. Andreas STEININGER (main responsibility)
E-Mail:
Homepage: https://ti.tuwien.ac.at/ecs/people/steininger/view

Types

Dissertation, Praktikum, Diplomarbeit

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