Practicals & Theses

List of practicals and theses at the Embedded Computing Systems Group (E182/2)

Efficient Interfacing Between Timing Domains

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Bakk.techn. Robert NAJVIRT, Dipl.-Ing. Dr.techn. Thomas POLZER, 03. 10. 2012

Within a closed timing domain the setup/hold requirements of all stateful elements can be safely met. Examples are a globally synchronous clock domain or an asynchronous handshake domain. Often it is, however, necessary to exchange signals between two (or more) such timing domains, which inevidently leads to metastability problems at the interfaces.
Your task will be to compile and compare existing solutions for this problem (assumptions, overheads, throughput, upset rate,...), using analytic models and analog simulations. The whole matrix of interfaces between synchronous systems, bounded delay systems and delay insensitive systems shall be covered, considering the diverse levels of synchrony (mesochronous, plesiochronous) and the asynchropnous handshake protocols (2-phase, 4-phase). Where required, new solutions shall be developed, and existing ones be improved. Applicable tools for the proof of concept as well as the assessment of the solutions' properties are simulation and FPGA prototype implementation.

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Effects of Stuck-at Faults on Delay-Insensitive Logic

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Bakk.techn. Robert NAJVIRT, 07. 08. 2012

In contrast to the state-based principle of synchronous logic, the operation of Delay Insensitive (DI) asynchronous logic is characterized by transitions. Therefore DI logic will generally stop operation in case of a stuck-at fault. In most cases this will lead to a "fail-stop" behavior, and the circuit may correctly continue its operation without the need for state recovery once the fault has been removed. Your task will be to identify all cases where this may not be true, i.e. the circuit will encounter one or more erroneous transitions before the deadlock, so that its state is currupted and need recovery. For the analysis theoretic consideration shall be combined with simulations, and finally some selected examples shall be demonstrated on an FPGA implementation.

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Fault Masking in Synchronous and in Asynchronous Logic -- A Comparison

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Bakk.techn. Robert NAJVIRT, 07. 08. 2012

A fault is said to be masked if it affects a circuit but never creates an erroneous state and hence stays ineffective. In synchronous logic it is agreed that faults can be masked on three levels, namely (1) electrical, (2) logical and (3) temporal level. While it can be expected that (1) and (2) work similarly in asynchronous logic, temporal masking will be very different: Instead of the rigid clock there is a flexible timing driven by completion detection. Preliminary investigations have revealed that skew plays a significant role here. Your task will be is a closer examination of this issue in both theory and practice: The masking effects shall be compared by their principles and determinating effects, and those effects shall be quantified for concrete practical examples (by means of simulations, demonstrators or timing analyses of existing designs), including electrical and logical masking.

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Confidence Analysis of a Fault Dictionary for Radiation Experiments

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Projektass.(FWF) MSc Varadan SAVULIMEDU VEERAVALLI, 07. 08. 2012

We are currently developing a target chip for an experimental analysis of the effect of radiation on VLSI circuits. Beyond the actual target circutis (basic functions like Muller C-elements, inverter chains, adders, ect.), this chip also comprises infrastructure for preprocesing and data collection. This infrastructure is also exposed to radiation and will therefore also experience upsets. Therefore it is equipped with redundancy and hence reports several views of the upset counts observed throughour a measurement period. We have already developed a fault dictionary that assigns to each set of reported count values the most probable physical scnario that caused it. However, there are always other, less probable scenarios that may lead to the same observation report. Your task will be a systematic analysis of the possible "less probable" interpretations, as well as a quantification of their relative probability. Based on these results our fault dictionary can then be enhanced by confidence values and further statistical characterization.

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