Practicals & Theses

List of practicals and theses at the Embedded Computing Systems Group (E182/2)

Development of a VxWorks Board Support Package for the Pandaboard

ECS: Dipl.-Ing. Dr.techn. Ulrich SCHMID, 23. 10. 2015

VxWorks (WindRiver) is a very popular real-time operating system for embedded platforms. The purpose of this project is to develop a Board Support Package (BSP) for the popular "Pandaboard" (, which is based on the Texas Instruments OMAP 4430 processor (dual-core ARM9). The development can start from the existing Linux-BSP for the Pandaboard and the existing VxWorks BSPs for OMAP3-based platforms.


Evaluation of operating systems for microcontrollers in wireless embedded systems

ECS: Projektass.(FWF) Dipl.-Ing. BSc Martin PERNER, 30. 01. 2014

The scope of this work is to evaluate the difference between operating systems, e.g., TinyOS and contiki, on battery powered AT86RF230 RCB motes, with regards to performance, code size and architectural design style.


Implementation Styles for Asynchronous Data Pipelines

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Bakk.techn. Robert NAJVIRT, 19. 10. 2012

Asynchronous Pipelines are typically controlled by a so-called Muller-Pipeline that handles the flow control in an elastic way. The control singnals created by the Muller-Pipeline are then connected to storage elements (registers) in order to manage the data flow appropriately. There are, however, many ways of doing this; like using both clock edges or just one, using flip flops or latches, by 4-phase or 2-phase protocol etc.
Your task will be to review the state of the art in this field, encompassing both bundled-data as well as quasi-delay insensitive pipelines. The result will be a comprehensive compilation of the methods, with each method being associated with the related pros and cons, preferred application cases as well as references and use cases from the literature. In the practical part of this work you will implement the methods and compare their performance, area overheads energy consumption etc.


Efficient Interfacing Between Timing Domains

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Bakk.techn. Robert NAJVIRT, Dipl.-Ing. Dr.techn. Thomas POLZER, 03. 10. 2012

Within a closed timing domain the setup/hold requirements of all stateful elements can be safely met. Examples are a globally synchronous clock domain or an asynchronous handshake domain. Often it is, however, necessary to exchange signals between two (or more) such timing domains, which inevidently leads to metastability problems at the interfaces.
Your task will be to compile and compare existing solutions for this problem (assumptions, overheads, throughput, upset rate,...), using analytic models and analog simulations. The whole matrix of interfaces between synchronous systems, bounded delay systems and delay insensitive systems shall be covered, considering the diverse levels of synchrony (mesochronous, plesiochronous) and the asynchropnous handshake protocols (2-phase, 4-phase). Where required, new solutions shall be developed, and existing ones be improved. Applicable tools for the proof of concept as well as the assessment of the solutions' properties are simulation and FPGA prototype implementation.


Limitations of DICE Latches in modern Technologies

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Projektass.(FWF) MSc Varadan SAVULIMEDU VEERAVALLI, 24. 08. 2012

DICE latches are latch cells that essentially use a ring of 4 inverters instead of 2 in the conventional latch. They have been proposed and used successfully for building radiation hard storage cells. However, it appears that for newer chip technologies they cannot provide sufficient radiation tolerance any more.
Your task will be to investigate the roots of this observation. In analog level simulations you will subject DICE cells implemented in different technologies (250nm ... 65nm) to radiation particle hits (by means of injecting current pulses). You will study how supply voltage, parasitic capacitances, transistor parameters etc. impact the cells' robustness against those faults. As a result you will be able to figure out down to which technology the DICE principle works satisfactory, and which measures might be taken to improve its robustness further.


Synchronization of Inputs into an Asynchronous Timing Domain

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Dipl.-Ing. Dr.techn. Thomas POLZER, 24. 08. 2012

Asynchronous circuits do not have a rigid clock signal, but still their operation is cyclic, and sometimes there is a need to synchronize external input signals to these cycles of operation. The function required for this purpose is similar to that of a synchronizer in the classical synchronous systems. In general, a Muller C-Element (or a chain thereof) or an arbiter can be used for this purpose.
Your task will be to compare these two options. For this purpose you will develop transistor-level simulation models (in SPICE) for both variants and perform comparisons with respect to residual upset rate, area, power consumption, latency etc. In addition it may turn out useful to develop analytical models to allow for a more direct and generic comparison.


Effects of Stuck-at Faults on Delay-Insensitive Logic

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Bakk.techn. Robert NAJVIRT, 07. 08. 2012

In contrast to the state-based principle of synchronous logic, the operation of Delay Insensitive (DI) asynchronous logic is characterized by transitions. Therefore DI logic will generally stop operation in case of a stuck-at fault. In most cases this will lead to a "fail-stop" behavior, and the circuit may correctly continue its operation without the need for state recovery once the fault has been removed. Your task will be to identify all cases where this may not be true, i.e. the circuit will encounter one or more erroneous transitions before the deadlock, so that its state is currupted and need recovery. For the analysis theoretic consideration shall be combined with simulations, and finally some selected examples shall be demonstrated on an FPGA implementation.


Fault Masking in Synchronous and in Asynchronous Logic -- A Comparison

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Univ.Ass. Dipl.-Ing. Bakk.techn. Robert NAJVIRT, 07. 08. 2012

A fault is said to be masked if it affects a circuit but never creates an erroneous state and hence stays ineffective. In synchronous logic it is agreed that faults can be masked on three levels, namely (1) electrical, (2) logical and (3) temporal level. While it can be expected that (1) and (2) work similarly in asynchronous logic, temporal masking will be very different: Instead of the rigid clock there is a flexible timing driven by completion detection. Preliminary investigations have revealed that skew plays a significant role here. Your task will be is a closer examination of this issue in both theory and practice: The masking effects shall be compared by their principles and determinating effects, and those effects shall be quantified for concrete practical examples (by means of simulations, demonstrators or timing analyses of existing designs), including electrical and logical masking.


Confidence Analysis of a Fault Dictionary for Radiation Experiments

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, Projektass.(FWF) MSc Varadan SAVULIMEDU VEERAVALLI, 07. 08. 2012

We are currently developing a target chip for an experimental analysis of the effect of radiation on VLSI circuits. Beyond the actual target circutis (basic functions like Muller C-elements, inverter chains, adders, ect.), this chip also comprises infrastructure for preprocesing and data collection. This infrastructure is also exposed to radiation and will therefore also experience upsets. Therefore it is equipped with redundancy and hence reports several views of the upset counts observed throughour a measurement period. We have already developed a fault dictionary that assigns to each set of reported count values the most probable physical scnario that caused it. However, there are always other, less probable scenarios that may lead to the same observation report. Your task will be a systematic analysis of the possible "less probable" interpretations, as well as a quantification of their relative probability. Based on these results our fault dictionary can then be enhanced by confidence values and further statistical characterization.


Can we trust the chips of the future?

ECS: Dipl.-Ing. Dr.techn. Andreas STEININGER, 07. 08. 2012

Recently concerns have been raised that some chips used in military applications have security problems: The suspect is that the fab has introduced a backdoor into the hardware. Announcements like this raise the question whether hardware is becoming prone to security threads like trojans, backdoors etc. that have so far been deemed to be "software only". Your task will be to investigate this issue in a literature study and develop a catalog of potential threads and related case reports.