Hardware Software CoDesign LU (WS 2015)



21. 12. 2015 Assignment and optimization criteria added
10. 11. 2015 Project template added
20. 10. 2015 Added overview slides, recommended reading, sample stream data
8. 10. 2015 Added task 1 assignment

General Course Information

Solution of a practical assignment from the field of HW-SW codesign - design, commissioning and optimisation of a complete system consisting of a processor, self-designed HW modules (FPGA), software (including drivers). Didactic procedure: The task consists of implementing the specified application on the FPGA. Typically, a pure software solution is created first, whose performance is highly unlikely to meet the specified minimum. Subsequently, weaknesses are identified in an appropriate analysis and systematically eliminated. Examples of necessary steps are:

  • Code optimization (C-level)
  • Rewriting code that is not optimised enough by the compiler in assembly
  • Adding application-specific instructions to perform common operations to the instruction set of the processor
  • Transferring functionality into hardware (designing (or finding) appropriate modules and integrating them)

The required knowledge includes in particular:

  • VHDL hardware design
  • C Software development
  • Computer architecture - instruction set, pipelining, memory organisation (SRAM, DRAM, I-/D-cache, scratchpad, register)
  • Understanding of algorithms - loop unrolling, pipelining, parallelization


At the beginning of the semester a small task needs to be solved in individual work. Its main goal is to make you familiar with the development platform provided (Terasic DE2-115, Display, Camera) as well as the used software tools (Altera Quartus, QSYS, NiosII IDE) and the processor (NiosII) with its connectivity options (Avalon bus). Who successfully solves this task, may enter the group phase, where in groups of three, the actual assignment is worked on. You can enter your desired group partners in MyTI. During the semester, there will be a midterm submission date, where you should provide a working solution (meeting the minimum performance requirement). The hardware/software complexity will be irrelevant for this submission. At that time, there will be a knowledge exchange session for which you should prepare a presentation (with slides) of your solution and proposed optimization targets to all other groups. The presentation is supposed to be 15 minutes long. At the end of the semester, you should submit your final solution which is not only working but also efficient (same performance with less resource utilization).

All submissions are organized as follows: Make an appointment for an exercise interview with the staff (personally or by ) and upload your project to MyTI no later than 24 hours before that appointment. Additionally, both the upload and the appointment may be no later than their respective deadlines. At the exercise interview, you will be tested for knowledge of your implementation details as well as details of the algorithms used in the application.


The individual work is rewarded with maximally 10 points, another maximally 40 points for the midterm submission. The final submission is rewarded with a maximum of 50 points (group members may be assessed differently).

The grading is: (S1) to 87.5 pt., (U2) to 75 pt., (B3) to 62.5 pt., (G4) to 50 pt., (N5) below.



5. 10. 2015  10:00 - 12:00
Course introduction Seminarraum Techn. Informatik
26. 10. 2015  23:59 Task 1 upload deadline MyTI
30. 10. 2015  16:00 Task 1 exercise interview deadline TILAB



General Conditions

  • TILAB Room: 1
  • Access times: Free working hours (first-come, first-served)
  • Lab accounts: Online at TILAB account portal (from 8. 10. 2015, only for TILAB cardholders)
  • TILAB access cards: Contact the if you have none, especially if you need one before 12. 10. 2015

Tutor Slots

There will be tutors helping you through the course. Details are to be added.


Introduction slides [pdf]
Task 1 (Individual) assignment [pdf]
Project template / Build environment [tar.gz]
Wireless receiver overview slides [pdf]
Raw test data (30s, 2.5 MSps, 100.5MHz center, 16bit/sample (8bit I + 8bit Q), used for above presentation, 150MB) [bin]
Ethernet streaming software (compile and run with as ethstream [<interface> [<MAC of FPGA board>]],
      needs privileges for raw socket - not on TILab pc, reads from stdin) [c]
Project template with ethernet & audio [tar.gz]
Optimization criteria [pdf]
Assignment [pdf]

Manuals / Recommended reading

Altera documentation website for Nios II [link]
    ↪  Documentation on Nios II, Qsys, IP cores, Build environment and much more including guides
Constraining and Analyzing Source-Synchronous Interfaces (just in case) [pdf]
Design Debugging Using the SignalTap II Logic Analyzer [pdf]
Board Manuals [zip]
Analog and Digital Communication Systems course at Stanford [link]
    ↪  Lab 5: Commercial FM very useful
Receiving RDS with the RTL-SDR blog by Oona Räisänen [link]
    ↪  Everything to go from demodulated FM to RDS data including code on GitHub
RDS specification [link]