Hardware Software CoDesign LU (WS 2014)



26. 2. 2014 Updated deadlines
11. 12. 2014 Added presentations date
12. 11. 2014 Added optimization criteria
11. 11. 2014 Added main task assignment

General Course Information

Solution of a practical assignment from the field of HW-SW codesign - design, commissioning and optimisation of a complete system consisting of a processor, self-designed HW modules (FPGA), software (including drivers). Didactic procedure: The task consists of implementing the specified application on the FPGA. Typically, a pure software solution is created first, whose performance is highly unlikely to meet the specified minimum. Subsequently, weaknesses are identified in an appropriate analysis and systematically eliminated. Examples of necessary steps are:

  • Code optimization (C-level)
  • Rewriting code that is not optimised enough by the compiler in assembly
  • Adding application-specific instructions to perform common operations to the instruction set of the processor
  • Transferring functionality into hardware (designing (or finding) appropriate modules and integrating them)

The required knowledge includes in particular:

  • VHDL hardware design
  • C Software development
  • Computer architecture - instruction set, pipelining, memory organisation (SRAM, DRAM, I-/D-cache, scratchpad, register)
  • Understanding of algorithms - loop unrolling, pipelining, parallelization


At the beginning of the semester a small task needs to be solved in individual work. Its main goal is to make you familiar with the development platform provided (Terasic DE2-115, Display, Camera) as well as the used software tools (Altera Quartus, QSYS, NiosII IDE) and the processor (NiosII) with its connectivity options (Avalon bus). Who successfully solves this task, may enter the group phase, where in groups of three, the actual assignment is worked on. You can enter your desired group partners in MyTI. During the semester, there will be one knowledge exchange session for which you have to prepare some slides to present your solution concepts to all other groups. The presentation is supposed to be 15 minutes long. At the end of the semester you need to submit the source code of your solution electronically and attend an exercise interview where you will be tested for knowledge of your implementation details as well as details of the algorithms used in the application.


The individual work is rewarded with maximally 15 points, another maximally 15 points for the presentation during the semester, the application along with the exercise interview is rewarded with a maximum of 70 points (i.e., group members may be assessed differently).

The grading is: (S1) to 87.5 pt., (U2) to 75 pt., (B3) to 62.5 pt., (G4) to 50 pt., (N5) below.



18. 12. 2014, 15:00 Presentations Seminarraum Techn. Informatik
15. 9. 2014 - 09. 10. 2014 Course registration electronic, via TISS.
06. 10. 2014, 10:00 - 12:00 Preliminary talk Seminarraum Techn. Informatik
26. 10. 2014, 23:59 MyTI upload deadline for Task 1
12. 2. 2015, 12:00 MyTI upload deadline for Main Task
13. 2. 2015 Last exercise interview appointment day
TILAB closes



General Conditions

  • TILAB Room: 1
  • Access times: Free working hours (first-come, first-served)
  • Lab accounts/TILAB access cards can be picked up at reasonable times in Robert Najvirt's office (Treitlstraße, 2nd floor).

Tutor Slots

During the following slot a tutor will be available in the lab room to answer your questions:

Monday, 15:00 - 17:00

At other times, do not hesitate to contact the tutors with questions at:
florian.huemer <at> student.tuwien.ac.at
markus.schuetz <at> student.tuwien.ac.at


Demo project [tar.gz]
Introduction slides [pdf]
Task 1 assignment [pdf]
Main task assignment [pdf]
Optimization criteria [pdf]


Altera documentation website for Nios II [link]
Nios II Hardware Development Tutorial [pdf]
My first Nios II Software Tutorial [pdf]
Avalon Interface Specifications [pdf]
Nios II Software Developer’s Handbook [pdf]
Nios II Custom Instruction User Guide [pdf]
Simulating Nios II Embedded Processor Designs [pdf]
Constraining and Analyzing Source-Synchronous Interfaces (just in case) [pdf]
Design Debugging Using the SignalTap II Logic Analyzer (for those who do not like the Agilent LA's in the lab) [pdf]
SD Card Specification [pdf]
Board Manuals [zip]