Hardware Software CoDesign LU (WS 2013)

News

 

15th Jan. 2013 Presentation and final submission details
2nd Dec. 2013 Added optimization criteria - sorry for the delay
5th Nov. 2013 Added Task 2 to assignment details
4th Nov. 2013 Added project template to downloads
14th Oct. 2013 Assignment details
16th Sept. 2013
Initial information

General Course Information

This lab course is devoted to the design and optimization of a combined HW/SW system. Our development environment consists of an FPGA board and associated peripheral components, such as a 5 megapixel camera and a 4.3 inch touchscreen display. The application that needs to be implemented has to be partitioned into SW and HW parts. The software runs on the small soft-core processor named NIOS II by Altera, the HW parts have to be implemented as hardware extension modules attached to the processor bus and/or custom instructions.

The work will be done in groups of three. You can enter your desired group partners when registering at MyTI. At the beginning of the semester a small "get-to-know" task has to be solved to make you familiar with our development environment. The solution of this task needs to be presented to our tutors. Then you can work on the main task for the rest of the semester. There will be no more intermediate deadlines, you can follow your own schedule. At the end of the semester you need to submit the source code of your solution electronically. Furthermore you have to prepare some slides to present your solution to all other groups. The presentation is supposed to be 15 minutes long. After each presentation we will have 5 minutes time for discussions.

For grading each group has to attend a short oral exam, where you need to show the running solutions to the lecturers and answer some questions relating to your implementation.

We recommend you to attend the associated lecture (VU HW/SW Codesign) in the same semester.

Grading

"get-to-know" task: 10pt
Presentation: 25pt
Final submission with oral exam: 65pt

Grade thresholds: 87,5pt 75pt 62.5pt 50pt
At the threshold, the better grade is given.

Schedule

 

Date Event Location
16th Sept. 2013 - 9th Oct. 2013
Course Registration
electronic, via MyTI.
1st Oct. 2013, 11:00 - 12:00 Preliminary talk HS 14A
8th Oct. 2013, 11:00 - 13:00 Task description HS 14A
14th Oct. 2013 Start of lab work, account pick-up
TILAB / ECS
25th Oct. 2013
Deadline for account pick-up
TILAB
28th Oct. 2013, 23:59
Deadline for submission of "get-to-know" task
electronic, via MyTI.
8th Nov. 2013
Deadline for showing "get-to-know" task to a tutor
TILAB
20th Jan. 2014 23rd Mar. 2014, 23:59
Deadline for submission of solution for main task
electronic, via MyTI.
21st Jan. 2014, 11:00 - 13:00 Solution presentations HS 14A
28 Mar. 2014 Deadline for oral exam ECSLAB

 

Laboratory

General Conditions

  • TILAB Room: 1
  • Access times: Free working hours (first-come, first-served)
  • Lab accounts/TILAB access cards can be picked up at reasonable times in Robert Najvirt's office (Treitlstraße, 2nd floor),
    starting 14th October 2013

Tutor Slots

During the following slots a tutor will be available in the lab room to answer your questions:

Monday 16:00 - 17:00

At other times, do not hesitate to contact the tutors with questions at:
florian.huemer <at> student.tuwien.ac.at
markus.schuetz <at> student.tuwien.ac.at

Downloads

Slides course introduction: [pdf]
Slides task description: [pdf]
Assignment details: [pdf]
Optimization criteria: [pdf]
Video file (SD card contents): [dirac]
Stream information: [soon]
SD block checksums: dec: [txt]   hex: [txt]
Project template with display driver: [tar.gz]

Manuals

Altera documentation website for Nios II [link]
Nios II Hardware Development Tutorial [pdf]
My first Nios II Software Tutorial [pdf]
Avalon Interface Specifications [pdf]
Nios II Custom Instruction User Guide [pdf]
Simulating Nios II Embedded Processor Designs [pdf]
Constraining and Analyzing Source-Synchronous Interfaces (just in case) [pdf]
Design Debugging Using the SignalTap II Logic Analyzer (for those who do not like the Agilent LA's in the lab) [pdf]
SD Card Specification [pdf]
Board Manuals [zip]
Dirac Specification [pdf]

TISS Information

Aim

practical application of the knowledge gained in the lecture experiences in design, operation and optimization of a combined HW/SW system

Subject

solution of a practical exercise from the area of HW-SW codesign (in groups) design, optimization and operation of a complete system comprising processor, custom-designed HW module (FPGA based), software (including drivers) Didactic concept: The desired functionality is specified through a given SW-only solution, which, however, has insufficient performance. The task is to identify the bottlenecks by means of suitable analyses and to systematically eliminate them. For this purpose it is necessary to move well selected functions to hardware, and develop and integrate respective hardware modules (a suitable programmable hardware target platform is provided along with a development environment). Possible optimization criteria are discussed in the associated lecture and are indicated beforehand. The task is assigned to small teams. In the end the individual results of the teams are compared and discussed.

Lecturer

  • Univ.Ass. Dipl.-Ing. Robert Najvirt
  • Univ.Ass. Dipl.-Ing. Thomas Polzer
  • Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Andreas Steininger

Homepage

https://ti.tuwien.ac.at/ecs/teaching/courses/hwsw_lu_WS2013