Hardware Software CoDesign LU (WS 2019)

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General Course Information

In this course you will solve practical assignments from the field of HW-SW codesign. This includes the design, commissioning and optimization of a complete system consisting of a processor, self-designed HW modules (FPGA) and software (including drivers). The main task is to implement a specific application on an FPGA whereat you have a lot of freedom on the implementation details. Typically, a pure software solution will be provided at the beginning, whose performance is far too low to meet the specified minimum. Subsequently, your task is to analyze the solution, identify weaknesses and enhance the performance, at least until the set goal is achieved. Examples of necessary steps are:

  • Code optimization (C-level)
  • Rewriting code in assembly when compilers do not achieve the optimum
  • Adding application-specific instructions to perform common operations to the instruction set of the processor
  • Transferring functionality into hardware (designing (or finding) appropriate modules and integrating them)

The required knowledge includes in particular:

  • VHDL hardware design
  • C Software development
  • Computer architecture - instruction set, pipelining, memory organisation (SRAM, DRAM, I-/D-cache, scratchpad, register)
  • Understanding of algorithms - loop unrolling, pipelining, parallelization

 

At the beginning of the semester a small task needs to be solved by each student individually. Its main goal is to get familiar with the provided development platform (Terasic DE2-115) as well as the used software tools (Altera Quartus, Platform Designer, NiosII IDE) and the processor (Nios II) with its interface options (Avalon bus, Custom Instructions).

After the introductory task, the group phase, where an assignment is solved in groups of three, begins. You will need to design and implement the application whereat you are free to choose the way to realize that in detail. To provide at least some guidance and to prevent that your design is heading in a completely wrong direction in early December a short mid-term presentation will be held with all groups present. These presentations should contain a thorough solution concept as well as a status report of the project. (Note that it is not required to have a fully working solution yet). You will be graded based on your concept and presentation. This presentation should also give you the opportunity to get feedback from other groups.

After that you are supposed to finalize the appointment until the end of the semester. To complete the task a final exercise interview in the lab is required. There you are supposed to present your solution and will be tested for your knowledge about the implementation details as well as the theoretical background (e.g. algorithms) of the application.

The introductory task is rewarded with 15 points, where at least 8 points must be achieved in order to successfully complete the course. For the mid-term presentation and the concept another 35 points can be earned. The final solution at the end of the semester is rewarded with a maximum of 50 points (note that group members may be assessed differently).

Solutions with with very good performance may be awarded bonus points.

Grading

In total, 100 points can be achieved.

The grading is: (S1) to 87.5 pt., (U2) to 75 pt., (B3) to 62.5 pt., (G4) to 50 pt., (N5) below.

Schedule

 

Date/Time Event Location
01.10.2019, 09:00 - 11:00
Course introduction Seminarraum Technische Informatik
04.10.2019, 10:00 - 12:00 Nios II/Qsys Introduction and Demonstration TILab Room 1(Treitlstraße 3/Hochparterre)
25.10.2019, 23:59 Deadline Get-To-Know Task
28.10. - 31.10.2019 Get-To-Know Task Interview
28.10.2019, 09:00-11:00 Introduction Main Task and Lecture Hardware Modeling Seminarraum Technische Informatik
2.12. - 6.12.2019 Midterm presentations ECS Library (Treitlstraße 3/2nd floor)
End of Jan. 2020 Final Deadline / Exercise Interview

 

Laboratory

General Conditions

  • TILab Room: 1
  • Access times: Free working hours (first-come, first-served)
  • Lab accounts: Online at TILAB account portal

Tutor Slots

A tutor is available to help you through the lab on TBA. You can also discuss your problems or ask for a meeting in the lab at hwswtut(at)ecs.tuwien.ac.at or in the TUWEL forum.

Manuals / Recommended reading

Intel Nios II (Gen 2) Documentation [link]

  • Processor Reference Guide [pdf]
  • Software Developer's Handbook [pdf]
  • Custom Instruction User Guide [pdf]
  • Instruction Set Reference (Processor Reference Guide, chapter 8)

Altera Avalon Interface Specification [pdf]
Integer Arithmetic IP Cores User Guide [pdf]
Constraining and Analyzing Source-Synchronous Interfaces (just in case) [pdf]
Design Debugging Using the SignalTap II Logic Analyzer [pdf]
Board Manuals [zip]