Hardware Software CoDesign LU (WS 2018)

Please also check the TUWEL course for further information.

General Course Information

Solution of a practical assignment from the field of HW-SW codesign - design, commissioning and optimisation of a complete system consisting of a processor, self-designed HW modules (FPGA), software (including drivers). Didactic procedure: The task consists of implementing the specified application on the FPGA. Typically, a pure software solution is created first, whose performance is highly unlikely to meet the specified minimum. Subsequently, weaknesses are identified in an appropriate analysis and systematically eliminated. Examples of necessary steps are:

  • Code optimization (C-level)
  • Rewriting code that is not optimised enough by the compiler in assembly
  • Adding application-specific instructions to perform common operations to the instruction set of the processor
  • Transferring functionality into hardware (designing (or finding) appropriate modules and integrating them)

The required knowledge includes in particular:

  • VHDL hardware design
  • C Software development
  • Computer architecture - instruction set, pipelining, memory organisation (SRAM, DRAM, I-/D-cache, scratchpad, register)
  • Understanding of algorithms - loop unrolling, pipelining, parallelization

 

At the beginning of the semester a small task needs to be solved in individual work. Its main goal is to get familiar with the development platform provided (Terasic DE2-115) as well as the used software tools (Altera Quartus, QSYS, NiosII IDE) and the processor (NiosII) with its connectivity options (Avalon bus, Custom Instructions).

After the introductory task, the project phase begins, where an assignment is solved in groups of three. At the beginning of December mid-term presentations will be held. These presentations should contain a well-thought-out solution concept as well as a status report of the project. (Note that it is not required to have a fully working solution yet). You will be graded based on your concept and presentation. This presentation should also give you the opportunity to get feedback from other groups.

To complete the project an exercise interview in the lab is required. There you will be tested for your knowledge about the implementation details as well as the theoretical background (e.g. algorithms) of the application. In addition, there will be a final presentation and discussion, where all groups present their work.

The introductory task is rewarded with 15 points, where at least 8 points must be achieved in order to successfully complete the course. For the mid-term presentation and the concept another 35 points can be earned. The final solution at the end of the semester is rewarded with a maximum of 50 points (note that group members may be assessed differently).

Solutions with with very good performance may be awarded bonus points.

Grading

In total, 100 points can be achieved.

The grading is: (S1) to 87.5 pt., (U2) to 75 pt., (B3) to 62.5 pt., (G4) to 50 pt., (N5) below.

Schedule

 

Date/Time Event Location
02.10.2018, 09:00 - 11:00
Course introduction FH4
04.10.2018, 10:00 - 12:00 Nios II/Qsys Introduction and Demonstration ECS Library (Treitlstraße 3/2nd floor)
31.10.2018 Deadline Get-To-Know Task / Exercise Interview ECS Lab (Treitlstraße 3/2nd floor)
13.12.2018, 10:00 - 12:00 Midterm presentations ECS Library (Treitlstraße 3/2nd floor)
End of Jan. Final Deadline / Exercise Interview ECS Lab (Treitlstraße 3/2nd floor)

 

Laboratory

General Conditions

  • TILAB Room: 1
  • Access times: Free working hours (first-come, first-served)
  • Lab accounts: Online at TILAB account portal

Tutor Slots

A tutor is available to help you through the lab on TBA. You can also discuss your problems or ask for a meeting in the lab at hwswtut(at)ecs.tuwien.ac.at.

Manuals / Recommended reading

Altera Nios II (Gen 2) Documentation [link]

  • Processor Reference Guide [pdf]
  • Software Developer's Handbook [pdf]
  • Custom Instruction User Guide [pdf]
  • Instruction Set Reference [pdf]

Altera Avalon Interface Specification [pdf]
Integer Arithmetic IP Cores User Guide [pdf]
Constraining and Analyzing Source-Synchronous Interfaces (just in case) [pdf]
Design Debugging Using the SignalTap II Logic Analyzer [pdf]
Board Manuals [zip]