Hardware Software CoDesign LU (WS 2016)



23. 11. 2016 Added tutor slots
23. 11. 2016 Updated group presentations time
30. 10. 2016 Main task assignment and template added
20. 10. 2016 Get-to-know template update (checker)

General Course Information

Solution of a practical assignment from the field of HW-SW codesign - design, commissioning and optimisation of a complete system consisting of a processor, self-designed HW modules (FPGA), software (including drivers). Didactic procedure: The task consists of implementing the specified application on the FPGA. Typically, a pure software solution is created first, whose performance is highly unlikely to meet the specified minimum. Subsequently, weaknesses are identified in an appropriate analysis and systematically eliminated. Examples of necessary steps are:

  • Code optimization (C-level)
  • Rewriting code that is not optimised enough by the compiler in assembly
  • Adding application-specific instructions to perform common operations to the instruction set of the processor
  • Transferring functionality into hardware (designing (or finding) appropriate modules and integrating them)

The required knowledge includes in particular:

  • VHDL hardware design
  • C Software development
  • Computer architecture - instruction set, pipelining, memory organisation (SRAM, DRAM, I-/D-cache, scratchpad, register)
  • Understanding of algorithms - loop unrolling, pipelining, parallelization


At the beginning of the semester a small task needs to be solved in individual work. Its main goal is to make you familiar with the development platform provided (Terasic DE2-115, Display, Camera) as well as the used software tools (Altera Quartus, QSYS, NiosII IDE) and the processor (NiosII) with its connectivity options (Avalon bus). Who successfully solves this task, may enter the group phase, where in groups of three, the main assignment is worked on. You can enter your desired group partners in MyTI.

All submissions are organized as follows: Make an appointment for an exercise interview with the staff (personally or by ) and upload your project to MyTI no later than 24 hours before that appointment. Additionally, both the upload and the appointment may be no later than their respective deadlines. At the exercise interview, you will be tested for knowledge of your implementation details as well as details of the algorithms used in the application.


In total, 100 points can be achieved.

The grading is: (S1) to 87.5 pt., (U2) to 75 pt., (B3) to 62.5 pt., (G4) to 50 pt., (N5) below.



Date/Time Event Location
3. 10. 2016  10:00 - 12:00
Course introduction Seminarraum Techn. Informatik
28. 10. 2016 Get-to-know task deadline  
12. 12. 2016 Midterm lab presentation deadline  
13. 12. 2016 9:00 13:00 Midterm group presentations  




General Conditions

  • TILAB Room: 1
  • Access times: Free working hours (first-come, first-served)
  • Lab accounts: Online at TILAB account portal

Tutor Slots

Two tutors are available to help you through the lab on Tuesdays 13:00 - 17:00 and on Wednesdays 9:00 - 13:00 (neighbouring room). You can also discuss your problems or ask for a meeting in the lab at hwswtut(at)ecs.tuwien.ac.at.


Introduction slides [pdf]
Get-to-know task assignment [pdf]
Get-to-know task template + assignment [tar.gz]
Main task assignment [pdf]
Main task template + assignment [tar.gz]

Manuals / Recommended reading

Quartus 16.0 ALTPLL fix [txt]
Altera documentation website for Nios II [link]
    ↪  Documentation on Nios II, Qsys, IP cores, Build environment and much more including guides
    ↪  e.g. Nios II Gen2 Hardware Development Tutorial [pdf]
Constraining and Analyzing Source-Synchronous Interfaces (just in case) [pdf]
Design Debugging Using the SignalTap II Logic Analyzer [pdf]
Board Manuals [zip]