Hardware Modeling (SS 2020)

TISS page 

News

2020/02/24 -- created homepage

Aim of lecture

Students finishing this course are able to

  • name the main differences between hardware and software designs
  • use basic VHDL commands and concepts
  • demonstrate the behavior of hardware modules described in VHDL
  • develop hardware designs with an internal state based on textual specifications
  • implement small hardware designs using the hardware description language VHDL
  • describe the development process of  a proper implementation strategy
  • discuss solutions for problems that appear in real world implementations
  • describe the tool design flow and useful mechanisms to control it
  • explain the single steps of the verification of a hardware implementation

Subject of course

The course is split into three parts:

1) In the first part we will take a closer look why hardware designs are reasonable to use in the first place and when they are best suited. We will also investigate the difference to software design and how hardware description languages may be of service.

2) After that we explore how hardware can be created, i.e., programmed. For this purpose we study the language VHDL, which is broadly used all around the globe. On a running example we explore the different design styles (concurrent, structural, sequential). Early in the lecture useful tools, i.e., Quartus for synthesis and QuestaSim for simulation, are introduced, such that you are able to explore VHDL on your own right from the start.

In the lecture the focus lies on understanding the basic concepts of VHDL. We are therefore going to take a look at how to properly write test benches, use the provided language constructs, implement state machines, use functions and procedures and handle different data types. These basic concepts are supported by examples provided in the TUWEL online course.

3) Finally when we know how to implement hardware, we take a look at how it can be designed in a reasonable fashion. We take a look at every step of the design flow: starting with specifications and ending at the final verification steps. In this part we shed light on how solutions can be achieved systematically and what advantages this yields. In addition real world problems are analyzed and the possibilities of VHDL to tackle these are explored. Besides that we also take a closer look at the tools and how they work and present methods to influence their behavior, with a strong focus on how to automatically verify your design.

Lecturer

Jürgen Maier 

General

This course provides an introduction to designing hardware using a hardware design language. It is recommended to attend the courses Digital Design before enrolling to this course as it is mandatory to understand how hardware is built and operates. We highly recommend to attend the course Digital Design and Computer Architecture in parallel to this course, as it allows you to immediately apply the content learnt in the lecture.

Didactic Concept

This lecture is using different state of the art didactic concepts, which are aimed to support the students and thus improve the learning experience. It has to be noted that all these supplements are optional but we highly recommend to use them to enhance your understanding.

Firstly remote learning is fully supported: The lecture can be watched live via the accompanying TUWEL online course (access after registration in TISS using the link provided in TISS). Furthermore all lectures are recorded and are available in general one day later for streaming in TUWEL as well. The main idea is to give you the opportunity to immediately program after learning the language. All the examples shown throughout the lecture will also be available for download, such that the students are able to experiment themselves. As it is essential to also solve problems yourself additional examples are provided in the TUWEL course, which enhance the examples shown in the lecture.

Secondly the content in the lecture will be examined interactively with the participants. Time students will be given time to develop own ideas, which can then be discussed with other students or in the plenum. For example students will be asked to answer interesting questions at first alone and afterwards in groups and then present their answer. As a support an online voting system (Presentr) will be used which allows anonymous participation. For this purpose please bring your own device (BYOD), e.g., mobile phone, laptop, tablet. Attendance is not mandatory but recommended.

We are still experimenting with several ideas and are eager to hear your feedback on the lecture and/or provided materials. Feedback is always possible via mail or anonymous in TISS and TUWEL.

Enrolling

To attend the lecture no enrollment in TISS is required, however it is mandatory to gain access to the accompanying TUWEL online course. We also recommend to subscribe to the LVA-Forum and News, as important information will also be published there. Note that for the exam you have to have finished the STEOP (Studien Eingangs und Orientierungsphase) which is however not mandatory to attend the lecture itself.

Grading

Grading results simply from a single exam, which is 60 minutes long and done on paper (no PC). A cheat sheet showing the syntax of VHDL will be provided (also available in TUWEL). For the exam understanding the presented concepts of hardware design and implementation is required. An overview of the content asked in the exam is provided here.

The grading scheme is as follows:

grade points
S1  96 - 85
U2  84 - 73
B3  72 - 61
G4  60 - 49
N5  48 - 0

Schedule

The lecture is heavily blocked at the beginning of the semester. This is necessary to give the participants of the lab course Digital Design and Computer Architecture the chance to quickly start their work (this was also demanded by previous semesters). More specifically the lectures will take place on Mondays, Tuesdays and Wednesdays 09:15-10:45 in EI10 starting on March 2nd and ending on March 23rd.

The complete lecture slides are available for download in the TUWEL course, although throughout the semester minor updates will be applied.

Other Resources

There are many interesting resources regard hardware design and VHDL on the web, most of them even freely accessible (within TU net). In the following a minor selection is shown in the following.

Books

A lot of different books are available in the TU library, many of those can even be accessed over the web. Please note that you have to be in the TU net for this to work. Examples are:

VHDL-Synthese (german): teaches basics of VHDL

The Designer's Guide to VHDL: also starts with teaching VHDL but gives more an overview of what to consider when designing hardware (second part of lecture)

Electronic Design Automation:  A comprehensive reference book regarding hardware design processes and VHDL.

Tools

It is not necessary to use the tools provided in the lab, although we recommend it as you also have to use these during the exam. Alternatives are open source software such as GHDL for example. Also several extensions and plug-ins for the terminal, vim, emacs and so forth exist. In addition it is possible to code in the browser at EDAplayground.

Handbooks

A great source are also the manuals provided for Quartus and the VHDL Standard 2008 (only accessible within the TU net).