Hardware Modeling (SS 2019)

TISS page



2019/02/25 -- created homepage

Aim of lecture

Students finishing this course are able to

  • name the main differences between hardware and software designs
  • use basic VHDL commands and concepts
  • demonstrate the behavior of hardware modules described in VHDL
  • develop hardware designs with an internal state based on textual specifications
  • implement small hardware designs using the hardware description language VHDL
  • describe the development process of  a proper implementation strategy
  • discuss solutions for problems that appear in real world implementations
  • describe the tool design flow and useful mechanisms to control it
  • explain the single steps of the verification of a hardware implementation


Subject of course

The course is split into three parts:

1) In the first part we will take a closer look why hardware designs are reasonable to use in the first place and when they are best suited. We will also investigate the difference to software design and how hardware description languages may be of service.

2) After that we explore how hardware can be created, i.e., programmed. For this purpose we study the language VHDL, which is broadly used all around the globe. On a running example we explore the different design styles (concurrent, structural, sequential). Early in the lecture useful tools, i.e., Quartus for synthesis and QuestaSim for simulation, are introduced, such that you are able to explore VHDL on their own right from the start.

In the lecture the focus lies on understanding the basic concepts of VHDL. We are therefore going to take a look at how to properly write test benches, use the provided language constructs, implement state machines, use functions and procedures and handle different data types. These basic concepts are supported by examples provided in the TUWEL online course.

3) Finally when we know how to implement hardware, we take a look at how it can be designed in a reasonable fashion. We take a look at every step of the design flow: starting with specifications and ending at the final verification steps. In this part we shed light on how solutions can be achieved systematically and what advantages this yields. In addition real world problems are analyzed and the possibilities of VHDL to tackle these are explored. Besides that we also take a closer look at the tools and how they work and present methods to influence their behavior, with a strong focus on how to automatically verify your design.


Jürgen Maier


Didactic Concept

The lecture will be recorded and available for streaming in the accompanying TUWEL online course afterwards. All the examples shown throughout the lecture will also be available for download, such that the students are able to experiment themselves. It is essential to also solve additionally provided examples to get a good understand of hardware design.

In the lecture the content will be examined interactively with the participants. Time will be given to develop own ideas, which can then be discussed with other students or in the plenum. To support this a simple online voting system will be used which allows anonymous participation. For this purpose please bring your own device (BYOD), e.g., mobile phone, laptop, tablet. Attendance is not mandatory but recommended.

We are still experimenting with several ideas and are eager to hear your feedback on the lecture and/or provided materials. Feedback is always possible via mail or anonymous in TISS and TUWEL.


To attend the lecture no enrollment in TISS is required, however it is mandatory to gain access to the accompanying TUWEL online course. We also recommend to subscribe to the LVA-Forum and News, as important information will also be published there.


Grading results simply from a single exam, which is 60 minutes long and done on paper (no PC). A cheat sheet showing the syntax of VHDL will be provided. For the exam understanding the presented concepts of hardware design and implementation is required. An overview of the content asked in the exam is provided here.

The grading scheme is currently changed and will be published later here

grade points


The lecture will be held on Wednesdays 09:15-10:45 in HS 17 and Fridays 13:15-14:45 in EI8. The complete lecture slides are available for download here. In the following an approximate schedule is shown (topics might be adapted according to the progress in class).

Day Date Time Location Topic
Wed 6.3.2019 09:15 HS 17

Preliminary & Introduction

Fri 8.3.2019 13:15 EI 8


Wed 13.3.2019 09:15 HS 17


Fri 15.3.2019 13:15 EI 8


Wed 20.3.2019 -- --

no lecture

Fri 22.3.2019 13:15 EI 8


Wed 27.3.2019 09:15 HS 17

Hardware Modeling

Fri 29.3.2019 13:15 EI 8

Hardware Modeling

Wed 3.4.2019 -- --

no lecture

Fri 5.4.2019 13:15 EI 8

Hardware Modeling

Wed 10.4.2019 09:15 HS17


Fria 12.4.2019 13:15 EI 8


Other Resources

 There are many interesting resources regard hardware desing and VHDL on the web, most of them even freely accessible (within TU net). In the following a minor selection is shown in the following.


A lot of different books are available in the TU library, many of those can even be accessed over the web. Please note that you have to be in the TU net for this to work. Examples are:

VHDL-Synthese (german): teaches basics of VHDL

The Designer's Guide to VHDL: also starts with teaching VHDL but gives more an overview of what to consider when designing hardware (second part of lecture)

Electronic Design Automation:  A comprehensive reference book regarding hardware design processes and VHDL.


It is not necessary to use the tools provided in the lab, although we recommend it as you also have to use these during the tests. Alternatives are open source software such as GHDL for example. Also several extensions and plug-ins for the terminal, vim, emacs and so forth exist.


A great source are also the manuals provided for Quartus and the VHDL Standard 2008 (only accessible within the TU net).