Hardware Modeling (SS 2018)

hwmod, VHDL

TISS page



20.2.2018: Dates and times of lectures changed

Aim of lecture

Acquisition of the ability to solve practical problems in a relevant field of computer engineering and to develop a proper documentation.


Subject of course

The course is split into three parts:

1) In the first part we will take a closer look why hardware designs are reasonable to use in the first place and when they are best suited. We will also investigate their properties and compare them to software based solutions.

2) After that we look at how hardware can be created, i.e., programmed. We study this using the language VHDL, which is broadly used all around the globe. On a running example we explore the different design styles (concurrent, structural, sequential). Early in the lecture useful tools, i.e., Quartus for synthesis and Modelsim for simulation, are introduced, such that the students are able to explore VHDL on their own right from the start.

In the lecture the focus lies on understanding the basic concepts of VHDL. We are therfore going to explain how to properly write test benches, use processes, implement state machines, use functions and procedures and handle different data types. These basic concepts are supported by examples provided in the TUWEL online course.

3) Since we now know how to create hardware, we take a look at how this can be done in a reasonable fashion. We start with a specification and investigate, based on an FPGA, how a proper development framework is selected, how the design can be partitioned, what to watch out for during coding and synthesis and finally how the design can be (automatically) simulated and verified.


Jürgen Maier


Background Info

The lecture will be recorded and available for streaming in the accompanying TUWEL online course. All the examples shown throughout the lecture will also be available for download, such that the students are able to experiment themselves. It is essential to also solve additionally provided examples to get a good understand of hardware design.

In the lecture the content will be examined interactively with the participants. Time will be given to develop own ideas, which can then be discussed with other students or in the plenum. Attendance is not mandatory but recommended.

The lecture was redesigned this summer term so we are still working on additional material, such as self assessment test in the style of multiple choice questions. If you want to participate just send us intersting questions or problems you expierienced and maybe even solved. We are also eager to hear your feedback on the lecture and/or provided materials.


To attend the lecture no enrollment is required, however to gain access to the accompanying TUWEL online course it is. We also recommend to subscribe to the LVA-Forum and News, as important news will also be published there.


Grading results simply from a single exam, which is 60 minutes long and done on paper (no PC). For the exam understanding the presented concepts of hardware design and implementation is required.


The lecture will be held on Wednesdays 09:15-10:45 in HS 17 and Fridays 13:15-14:45 in EI8.

Day Date Time Location Topic
Fri 2.3.2018 13:15 EI 8 Preliminary & Introduction
Wed 7.3.2018 09:15 HS 17

VHDL basics

concurrent design style

Fri 9.3.2018 13:15 EI 8

test benches

structural design style

sequential design style

Wed 14.3.2018 09:15 HS 17

design styles overview

state machines

improved test benches

Fri 16.3.2018 13:15 EI 8

data types and operators

function and procedures

Wed 21.3.2018 -- --

no lecture

Fri 23.3.2018 -- --

no lecture

Wed 11.4.2018 09:15 HS 17

Hardware Modeling Introduction

design phase

Fri 13.4.2018 13:15 EI 8

coding & synthesis

Wed 18.4.2018 -- --

no lecture

Fri 20.4.2018 13:15 EI 8


Wed 25.4.2018 09:15 HS17


Fria 27.4.2018 13:15 EI 8


Other Resources

 There are a lot of intersting resources on the web:


A lot of different books are available in the library, many of those can even be accessed over the web. Please note that you have to be in the TU net for this to work. Examples are:

VHDL-Synthese (german): teaches basics of VHDL

The Designer's Guide to VHDL: also starts with teaching VHDL but gives more an overview of what to consider when designing hardware (second part of lecture)


It is not necessary to use the tools provided in the lab, although we recommend it as you also have to use these during the tests. Alternatives are open source software such as GHDL for example. Also several extensions and plug-ins for the terminal, vim, emacs and so forth exist.


A great source are also the manuals provided for Quartus and the VHDL Standard 2008 (only accessible within the TU net).