Hardware Modeling (WS 2016)

Dates and Conditions

All lectures are given in October/November on Thursdays and Fridays, starting with Oct 6th. There will be 8 or 9 lectures.
Lecture times:

  • Tuesdays: 11:00 c.t. to 13:00 (FHHS4)
  • Thurdays: 14:00 s.t. to 16:00 (EI4)
  • Fridays: 11:00 s.t. to 13:00 (EI10)

For attending this course, you are required to registers at TISS.

Lecture dates:

Th. 06.10.2016

Fr. 07.10.2016

Th. 13.10.2016

Tu. 18.10.2016 - Repeating the lecture from 07.10.2016

Fr. 21.10.2016

Tu. 25.10.2016

Th. 27.10.2016

Fr. 28.10.2016

Fr. 04.11.2016

Lecture Contents

An overview of different aspects of hardware modelling is given. The main part of the lecture focuses on (i) the hardware description language VHDL, (ii) FPGA design flow, (iii) functional verifcation using simulation.

Course materials:
Registered students can find the course material in TISS.


The grades are based on an written exam after the lecture. The exam will cover all topics of the lecture and will contain theory questions as well as small VHDL assignments.

Go to the course site on TISS for exam registration.



Theoretical introduction in modeling and specification of integrated circuits. Learning the design flow based on a high-level modeling language (VHDL). Experiencing the differences between hardware design and software design (concurrency, etc.).


Hardware description in a high-level language (at the example of VHDL), syntax, abstraction levels, hierarchy; Description of temporal relations: concurrency, synchronity, handshake; Design flow, verification, libraries, tools; Systematic, maintainable hardware design: design-rules,  documentation; Didactic concept: Lecture dates concentrated in one month. Theoretical lessons accompanied by specific application examples. Introduction into design tools during the lecture.


Univ.Ass. Dipl.-Ing. Dr.techn. Thomas Polzer
Univ.Ass. Dipl.-Ing. Robert Najvirt



Letztes Semester

Hardware Modelling (WS2015)