Digital Design (WS 2021)
Termin und Ort
Im WS 2021 wird die Vorlesung an folgenden Terminen und Orten abgehalten:
| Mo | 11:15 - 13:00 | online |
| Fr | 11:15 - 13:00 | online |
Bitte melden Sie sich für die LVA in TISS an, damit Sie für kurzfristige Mitteilungen erreichbar sind. Damit erhalten Sie auch Zugang zu den Unterlagen sowie zum Link für die Online-Plattform.
Vorbesprechung
Die Vorbesprechung findet am 4. Oktober 2021 um 11:15 statt (online)
Vorlesungsinhalt
- Grundlagen
- ASIC-Fertigung
- CMOS-Logik
- Design-Flow
- Speichertechnologien
- ASIC-Zieltechnologien
- Temperatur & Verlustleistung
- Datenblatt-Angaben
- Synchrones Design & Metastabiliät
- Defekte
- Test
- Logikanalysator
Fragen, Vorschläge, Anregungen und Kritik zu Vorlesung und Übung richten Sie bitte per eMail an: dide@ecs.tuwien.ac.at
TUWIS Info
Aim
Students having passed this course can
- desrcibe the design and fabrication flows of a digital CMOS ASIC, justify their steps and list the challenges involved in them,
- correctly apply the abstraction of a field-effect transistor as a switch and use it to explain the basic function of simple logic gates,
- describe implementation and operation of fundamental function blocks of digital logic, and apply them properly,
- design a (combinational or simple sequential) digital circuit solving a given problem, and compare implementation options
- identify, in an application, the limits of the models and abstractions used in digital design, and appropriately account for them
- relate defects and functional faults in a digital integrated circuit to their potential cause in the design and fabrication flow, and describe the effect ot the most relevant parameters of influence in a qualitative and, where possible, a quantitative way.
Subject
- logic optimization
- structure and specifications of logic gates
- basic arithmetic circuits (adder, multiplier)
- I/O features (schmitt trigger, open collector, ...)
- power dissipation and cooling
- synchronous logic, limitations, state machines
- metastability
- memory types
- VLSI design flow
- simulation of hardware
- target technologies for VLSI designs
- chip manufacturing process
- defects and testing
Lecturer
Dipl.-Ing. Dr.techn. Andreas Steininger