Digital Design (SS 2017)

Termin und Ort

Im SS 2017 wird die Vorlesung an folgenden Terminen und Orten abgehalten:

 

Mo   10.15 - 12.00 HS13
Fr    11.15 - 13.00 EI10

Für die Teilnahme an der Vorlesung ist keine Anmeldung erforderlich, wohl aber für die Vorlesungsprüfung.

An folgenden Terminen entfällt die Vorlesung: 16.10., 20.10.

Bitte abonnieren Sie die LVA im TISS, damit Sie für kurzfristige Mitteilungen erreichbar sind.

 

Vorbesprechung

Die erste Vorlesung findet dann am 1. Oktober 2017 um 10:15 im HS13 statt.

 

Vorlesungsinhalt

  1. Grundlagen
  2. ASIC-Fertigung
  3. CMOS-Logik
  4. Design-Flow
  5. Speichertechnologien
  6. ASIC-Zieltechnologien
  7. Temperatur & Verlustleistung
  8. Datenblatt-Angaben
  9. Synchrones Design & Metastabiliät
  10. Defekte
  11. Test
  12. Logikanalysator

 


 

Fragen, Vorschläge, Anregungen und Kritik zu Vorlesung und Übung richten Sie bitte per eMail an:  dide@ecs.tuwien.ac.at

TUWIS Info

Aim

Students having passed this course can

* desrcibe the design and fabrication flows of a digital CMOS ASIC, justify their steps and list the challenges involved in them,

* correctly apply the abstraction of a field-effect transistor as a switch and use it to explain the basic function of simple logic gates,

* describe implementation and operation of fundamental function blocks of digital logic, and apply them properly,

* design a (combinational or simple sequential) digital circuit solving a given problem, and compare implementation options

* identify, in an application, the limits of the models and abstractions used in digital design, and appropriately account for them

* relate defects and functional faults in a digital integrated circuit to their potential cause in the design and fabrication flow, and describe the effect ot the most relevant parameters of influence in a qualitative and, where possible, a quantitative way.





Subject

* logic optimization
* structure and specifications of logic gates
* basic arithmetic circuits (adder, multiplier)
* I/O features (schmitt trigger, open collector, ...)
* power dissipation and cooling
* synchronous logic, limitations, state machines
* metastability
* memory types
* VLSI design flow
* simulation of hardware
* target technologies for VLSI designs
* chip manufacturing process
* defects and testing

Didactic concept: This is a classical lecture. The whole material is presented in lectures, in theory as well as with a relation to practical application. Example calculations are made during the lecture to facilitate the preparation for the final exam, and to show quantitative results and relations. During one lecture an experiment is made showing the "speed signal propagation" in an intuitive way. The lecture slides including numerous animations are available on the homepage. For the preparation of the final exam a collection of past exams is also available.





Lecturer

Ao.Univ.Prof. Dr. Andreas Steininger

Homepage

http://ti.tuwien.ac.at/ecs/teaching/courses/didevo/