Digital Design and Computer Architecture (SS 2019)
Aim
The central aims of the lab are: (1) illustrating the design flow of a digital ASIC (FPGA) at a practical example, first use of the typical tools (2) gaining experience with the handling of a logic analyzer, exploration of its possibilities and limitations (3) gaining first experience with the design and debugging of digital circuits on the example of a processor which is to be imlemented
Subject
contents of the lectures "Digital Design", "Hardware Modeling" and "Computer Organzation and Design", in particular design flow (synthesis & simulation) as well as testing & debugging of a VHDL design, practical handling of digital measurement instruments, architecture of a processor
Lecturer
Univ.Ass. Dipl.-Ing. Florian Huemer
Univ.Ass. Dipl.-Inform. Florian Kriebel
Univ.Ass. Dipl.-Ing. Dipl.-Ing. Jürgen Maier
Univ.Prof. Dr.-Ing. Muhammad Shafique
Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Andreas Steininger
Homepage
https://ti.tuwien.ac.at/ecs/teaching/courses/ddca19/
News
| Date | Change |
|---|---|
| 26.02.2019 | Course Website for SS2019 online, added dates for Preliminary Talk |
| 05.03.2019 | Tutor slots added |
General
The lab course is mandatory in the Computer Engineering Bachelor curriculum. The course is recommended for students in the fourth semester. Additionally the course may be chosen by students of the Data Engineering & Statistics, Software & Information Engineering (Specialization field: Software Engineering) and Medical Informatics Bachelor, and the Computer Engineering Master curriculum as elective course. The admission to the course is restricted by the STEOP regulation. It is recommended to attend the courses Digital Design before enrolling to this course. The courses Hardware Modeling and Computer Organization and Design can be attended in parallel to this course.
A registration via TISS is mandatory. The course will be managed using TUWEL. The first part of the course (exercises 1-2) is done individually, while the second part (exercises 3 and 4) are done in groups of three. You may specify the preferred group partners in TUWEL after the midterm exam. The groups will be formed automatically in TUWEL after the midterm exam. Afterwards the group partners will be visible there.
Syllabus
The lab course is based on the above mentioned lectures and therefore it is recommended that only students who have already attended the lectures enroll to this course. The aim of the course is to collect first practical experiences in writing simple structural and behavioral VHDL code, using the logic analyzer, simulating and debugging VHDL designs, designing state machines and the implementation of a simple, pipelined processor.
The lab course is structured into four tasks: The first two tasks have to be solved individually while the last two have to be solved together with your group partners. Each individual/group has a predefined quota of supervised lab time which has to be reserved via TUWEL. In these slots a tutor is present in the lab. Outside of the supervised slots the usage of the lab is on first come, first serve basis. For each task a protocol has to be written and submitted via TUWEL.
Grading
Your grade will be calculated from the following three parts:
- 4 lab tasks (50 %)
- A midterm exam (25 %)
- A final exam (25 %)
The midterm and final exams are written on individual (not group!) basis. The midterm exam consists of purely practical assignments. It will be concerned with simulation, debugging and measuring a test circuit as well as with writing VHDL code (as in task 1 and 2). The final exam consists of practical and theoretical assignments and will be mainly based on computer architecture (tasks 3 and 4).
After finishing a lab task, you can ask a Tutor to check your results. This check will give you feedback, if your results are complete and correct. The protocol must comply with the predefined templates. These templates will be provided on the course homepage. The protocol must be submitted via TUWEL before the corresponding deadline. Late submissions cannot be accepted. After submitting your protocol, you have to show the protocol and the working design to a Tutor. This can happen before the deadline (if you have finished and uploaded your design already) or in your first lab-slot after the deadline. The Tutor will check the completeness of your solution and will forward your design and protocol to the staff for grading.
Grading scheme:
| S1 | > 89% |
| U2 | 76%-88% |
| B3 | 63%-75% |
| G4 | 51%-62% |
| N5 | < 51% |
Schedule
| 14.02.2019 - 05.03.2019 | Registration via TISS |
| 04.03.2019 14:00 | Preliminary talk (EI 11 Geodäsie HS) |
| 11.03.2019 15:00 | Intro (optional) (EI 4 Reithoffer HS ) |
All other dates and deadline are announced in TUWEL!
Laboratory
The TILAB laboratory is located at Treitlstrasse 3 (Hochparterre). Room 1 (and in part Room 2) is reserved for this course. There will be supervised lab-slots available on following weekly schedule, excluding holidays and days on which the lab is closed or otherwise reserved. Reservations for the supervised TILAB slots can be made in TUWEL. If you don't have a reservation for a particular lab slot or if you come to the lab outside of the supervised slots, we have a first come, first served policy for the lab computers.
Schedule:
| Day | Time |
|---|---|
| Monday |
13:00 - 17:00 |
| Tuesday |
09:00 - 13:00 |
| Wednesday |
16:00 - 20:00 |
| Thursday |
11:00 - 15:00 |
| Friday |
09:00 - 13:00 |
Task Assignments & Protocol Templates
Please consider the protocol template as part of the assignment - download it before you start working so that you do not forget to save all requested data and screenshots.
The assignments can be downloaded from the TUWEL course.
Software
- Quartus Design Tools
- ModelSim (Attention: Download ModelSim*-Intel® FPGA Starter Edition)
GIT Repository
In case you want to share a GIT repository with your group members, you can create a repository directory in one of the members home directory. In order to give the other group members access to this directory you have to change to linux group of this directory to "ddcagrp<NN>", where NN stands for your group number as assiged in TUWEL (you can also find out your groupname with the linux command "id"). Furthermore you need to assign read/write permissions the group on this directory. Consider the command sequence below:
cd $HOME mkdir repo chgrp ddcagrp99 repo chmod g+rws repo
Now a GIT repo can be created within the "repo" directory.
Other group members can then access this repository using the following GIT command (<username-hoster> refers to the username of the group member, who created the repo directory above):
git clone ssh://<myusername>@ssh.tilab.tuwien.ac.at/homes/<username-hoster>/repo
Alternatively, you can use a shell script for automating the generation of a GIT repository: [mkgitrepo.sh]
This script can be executed by the group member who hosts the repository on his lab account. It will create a directory as above, assign the correct permissions and create an empty GIT repository. The script needs to be executed with the following parameters:
./mkgitrepo.sh ddcagrp<NN> <directory name for repository>