Advanced Digital Design (WS 2021)

The course focuses on advanced timing issues in digital design. The need for design methodologies is elaborated, and alternatives to the traditional synchronous design style are discussed, such as "globally asynchronous locally synchronous (GALS)" and purely asynchronous styles (bounded delay as well as delay insensitive). The scope spans from the underlying theory to practical design flow. In context with synchronous design and GALS, metastability issues are treated in much detail.

General Information about the Course


The course comprises a mix of lecture blocks and exercise blocks. The latter are concerned with discussing homeworks (results of questions/calculations). The labs are optional as an extra course (LU) that can be taken in conjunction with the lecture/exercise (VU). The lecture exercise can be attended without taking the lab, but not vice versa.

The course materials (lecture slides, homework assignments, auxiliary material) can be downloaded in TUWEL. The solutions must be provided as .pdf and uploaded to TUWEL on the day before the respective exercise block, before 12:00 noon.

 

Course Dates

Please register for the course in TISS and TUWEL

Introduction and Overview of Courses :

  • An overview of the Courses offered by our Group in the winter term 20/21 will be given in an introductory lecture on Friday, Oct 5   at 9:00 online or in presence (see TISS) .

Regular Lectures and Exercises:

  • The regular lecture date is Tuesday  9:00 c.t. to 11:00 (Room Fav 1).
  • In addition there are extra slots for the presentation of the homeworks. These will be on
    Nov 25, Dec 16 and Jan 13, from 14:00 to 16:00

 

Final Exam:

  • The final written exam will be fixed during the course.

 

Course Materials


The lecture slides, assignments as well as supplementary material are available in TUWEL.

For the lectures on Asynchronous Logic Design the following text book is additionally recommended:

Jens Sparso and Steve Furber
Principles of Asynchronous Design -- A Systems Perspective
Kluwer Academic Publishers, 2001

For students a free .pdf version of chapters 1 - 7 of this book is available at Jens Sparso's homepage.

A very good survey on asynchronous logic can also be found in the following articles:
S.M. Nowick, M. Singh, Asynchronous Design—Part 1: Overview and Recent Advances, IEEE Design & Test, vol 32(3) and
S.M. Nowick, M. Singh, Asynchronous Design—Part 2: Systems and Methodologies , IEEE Design & Test, vol 32(3).

A very good introduction and survey of static pipelines can be found in our students' project report on CLAP. Further details about Asynchronous Pipelines are given in the survey article S.M. Nowick, M. Singh, High-Performance Asynchronous Pipelines: An Overview, IEEE Design & Test of Computers, vol 28(5), 2011

A comparison of delay-insensitive codes as well as an efficient method for building completion detectors can be found in conference papers that resulted from one of our students' projects.

For additional reading about Synchronizers the following book

David J. Kinniment and Alex Yakovlev
Synchronization and Arbitration in Digital Systems
Wiley

as well as the article Ran Ginosar, Metastabilty and Synchronizers: A Tutorial, IEEE Design & Test of Computers, vol 28(5) , 2011

are recommended. A comprehensive survey on synchronizer techniques is given in the Master thesis by Robert Kutschera.

 

Grading


The grading for the lecture will be based on the following scheme

  • exercises (quality of submitted solutions, presentation of solution): 40%
  • written exam: 40%
  • the remaining 20% can be attained through contributions to discussions during lectures and exercise discussions


For a positive grade, at least 40% of the achievable credits in exam and exercises must be reached, as well as at least 50% overall; the borderlines for the other grades will be at 62.5%, 75%, 87,5%, accordingly.

 

Aim

the following competences shall be conveyed:

  • deal with challenging (timing) issues in digital design (esp. clock domain crossing)
  • understand the theoretical underpinningsof the synchronous design style and its alternatives
  • choose the appropriate style for a given problem
  • understand the involved limitations

Subject

  • basic concept and limitations of synchronous design
  • metastability: causes and effects, modelling, MTBU estimation and measurement
  • design and implementation of synchronizers for different settings
  • GALS-Systems (timing domain crossing, pausable clocking)
  • internal design, function and limitations of the basic building blocks of asynchronous design: Muller C-Element and Mutual Exclusion Element
  • asynchronous design methods (bundled data, delay insensitive), handshake principles (2-phase/4-phase) and timing models (bundled data, delay insensitive,...)
  • fundamental description methods for asynchronous design
  • comparison of synchronous and asynchronous logic

Lecturer

Dipl.-Ing. Dr.techn. Steininger Andreas

Homepage

https://ti.tuwien.ac.at/ecs/teaching/courses/adide_ws20/