Advanced Digital Design (WS 2017)

The course focuses on advanced timing issues in digital design. The need for design methodologies is elaborated, and alternatives to the traditional synchronous design style are discussed, such as "globally asynchronous locally synchronous (GALS)" and purely asynchronous styles (bounded delay as well as delay insensitive). The scope spans from the underlying theory to practical design flow. In context with synchronous design and GALS, metastability issues are treated in much detail.

General Information about the Course

The course comprises a mix of lecture blocks, exercise blocks and labs. The latter two are concerned with discussing homeworks (results of questions/calculations and circuit designs, respectively). The labs are optional as an extra course (LU) that can be taken in conjunction with the lecture/exercise (VU). The lecture exercise can be attended without taking the lab, but not vice versa.

The course materials (lecture slides, homework assignments, auxiliary material) can be downloaded in TUWEL. The solutions must be provided as .pdf and uploaded to TUWEL on the day before the respective exercise block, before 12:00 noon.


Course Dates

An introduction into scope and organization of the course will be given on Wednesday, October 4, 2017 at 10.00 s.t. in seminar room BA 02A
Please register for the course in TISS


Regular Lectures and Exercises:

  • The regular lecture date is Wednesday  10:00 c.t. to 12:00 in seminar room BA 02A.
  • In addition there are extra slots for the presentation of the homeworks and (optional) lab exercises, namely on selected Tuesdays 13:00 c.t. to 15:00 in seminar room TI
    (for details see table below)


Final Exam:

  • tbd




Course Materials (continuously extended)

The lecture slides will be available in TUWEL.

For the lectures on Asynchronous Logic Design the following text book is additionally recommended:

Jens Sparso and Steve Furber
Principles of Asynchronous Design -- A Systems Perspective
Kluwer Academic Publishers, 2001

For students a free .pdf version of chapters 1 - 7 of this book is available at Jens Sparso's homepage.

A very good survey on asynchronous logic can also be found in the following articles:
S.M. Nowick, M. Singh, Asynchronous Design—Part 1: Overview and Recent Advances, IEEE Design & Test, vol 32(3) and
S.M. Nowick, M. Singh, Asynchronous Design—Part 2: Systems and Methodologies , IEEE Design & Test, vol 32(3).

A very good introduction and survey of static pipelines can be found in our students' project report on CLAP. Further details about Asynchronous Pipelines are given in the survey article S.M. Nowick, M. Singh, High-Performance Asynchronous Pipelines: An Overview, IEEE Design & Test of Computers, vol 28(5), 2011

A comparison of delay-insensitive codes as well as an efficient method for building completion detectors can be found in conference papers that resulted from one of our students' projects.

For additional reading about Synchronizers the following book

David J. Kinniment and Alex Yakovlev
Synchronization and Arbitration in Digital Systems

as well as the article Ran Ginosar, Metastabilty and Synchronizers: A Tutorial, IEEE Design & Test of Computers, vol 28(5) , 2011

are recommended. A comprehensive survey on synchronizer techniques is given in the Master thesis by Robert Kutschera.




Date Topic Materials
October 11,        10:00 - 12:00 1 - Organization, The Role of Time  
October 18,        10:00 - 12:00 2 - Timing Model & Synchronous Design  
October 25,        10:00 - 12:00 3 - Metastability Models  
November 7,      13:00 - 15:00 RA - Discussion Exercise 1  
November 8,      10:00 - 12:00 3 - Metastability Measurement, Synchronizers  
November 22,    10:00 - 12:00 4 - GALS Design, Pausable Clocks  
November 29,    10:00 - 12:00

5 - Asynchronous Design - Principles, Bundled Data

December 5,      13:00 - 15:00 DA - Discussion Design 1  
December 6,      10:00 - 12:00 6 - Delay Insensitive Asynchronous Design Styles  
December 12,    13:00 - 15:00 RB - Discussion Exercise 2  
December 13,    10:00 - 12:00 7 - Asynchronous Data-flow Structures  


January    9,      13:00 - 15:00

DB - Discussion Design 2

January 10,       10:00 - 12:00

8 - Synthesis of Control Circuits

January 16,       13:00 - 15:00 RC - Discussion Exercise 3  
January 17,       10:00 - 12:00 9 + 10 - Description Methods for asynchronous design /asynchronous EDA  
January 23,       13:00 - 15:00 DC - Discussion Design 3  
January 31,       10:00 - 12:00 Final Exam (Library 182-2, Treitlstrasse 2nd floor)  



The grading for the lecture will be based on the following scheme

  • exercises (quality of submitted solutions, presentation of solution): 40%
  • written exam: 40%
  • the remaining 20% can be attained through contributions to discussions during lectures and exercise discussions

For a positive grade, at least 40% of the achievable credits in exam and exercises must be reached, as well as at least 50% overall; the borderlines for the other grades will be at 62.5%, 75%, 87,5%, accordingly.


For the lab the grading will be as follows:


  • quality of submitted solutions: 75%
  • presentation of solutions: 25%

Again at least 50% overall must be attained for a positive grade; the borderlines for the other grades will be at 62.5%, 75%, 87,5%, accordingly.



the following competences shall be conveyed:

  • deal with challenging (timing) issues in digital design (esp. clock domain crossing)
  • understand the theoretical underpinningsof the synchronous design style and its alternatives
  • choose the appropriate style for a given problem
  • understand the involved limitations


  • basic concept and limitations of synchronous design
  • metastability: causes and effects, modelling, MTBU estimation and measurement
  • design and implementation of synchronizers for different settings
  • GALS-Systems (timing domain crossing, pausable clocking)
  • internal design, function and limitations of the basic building blocks of asynchronous design: Muller C-Element and Mutual Exclusion Element
  • asynchronous design methods (bundled data, delay insensitive), handshake principles (2-phase/4-phase) and timing models (bundled data, delay insensitive,...)
  • fundamental description methods for asynchronous design
  • comparison of synchronous and asynchronous logic


Dipl.-Ing. Dr.techn. Steininger Andreas