Advanced Digital Design Lab (WS 2020)

This lab course is complementary to the VU Advanced Digital Design.

General Information about the Course

This lab complements the lecture and exercises of the course VU Advanced Digital Design by practical (FPGA) design exercises that give the student first experience with asynchronous design in practice.


the following competences shall be conveyed:

  • practically apply the knowledge obtained from the associated lecture
  • practically apply the relevant design methods
  • correctly respect the limitations of the chosen method in a practical application


contents of the associated lecture (182.755)


Dipl.-Ing. Dr.techn. Steininger Andreas


For this course distance learning technologies is heavily used. Except for one measurement (as will be explained later) everything will be carried out remotely. This does, however, not mean that you have to work completely on your own. Since we know how important it is to get in touch with the lecturers we provide several ways you can approach us:

  • For non time critical questions that may also be interesting for your colleagues we suggest to use the Questions & Remark forum in TUWEL. Feel free to comment/answer the questions of your colleagues or start discussions.
  • If the matter is more urgent or the forum does not seem the right way to go we also provide a TU Chat Channel. Of course this channel is not solely reserved for student-lecturer communication so feel free to use it for further discussions.
  • Clearly in some situations talking is much more fruitful than typing. Therefore we also offer remote web conferences. If you want to speak to a lecturer state your demand in the TU Chat Channel and we will then schedule a meeting with you (and your group).

Throughout this course you have to develop three different designs and download them to an FPGA. For this purpose you will get an TILab account where our regular tools (Questa, Quartus) are available. Note: If you connect using ssh -XC application started on the remote PC will show up including the GUI on your screen. It is also possible to download free versions of these tools from the web pages of the respective developers. For downloading your design to the FPGA we provide two possibilities:

  • TIsdanceLab: This system we install in the TILab allows to exclusively reserve a lab PC, which is connected to an FPGA, download your solution and observe the behavior via an attached web cam. The respective TIsdanceLab manual is available in the TUWEL course. We advise you to come prepared (fully compiled .sof file) since the available slots are time limited, since multiple lectures will share the resources.
  • Lend Development Boards: It is also possible to lend one development board per group for the duration of the winter term. If you are interested in borrowing a boards contact the lecture staff on the TU Chat Channel.

Although we have a highly evolved remote setup in Design 1 you are required to make measurements with an oscilloscope. We regard this as highly necessary since only in this way it is possible to fully experience and understand the glitches in the design. Unfortunately these measurements can only be done in person in the TILab in Room 1. In TISS you can register for 5 groups, whereat each group has unlimited access to the lab on one day per week. Note that a registration in TUWEL does not automatically registers you in TISS, nor the other way around! TISS and TUWEL groups thus do not necessarily have to coincide, however, it might be a good idea to do so. We want to strengthen on this occasion that only the persons registered in TISS for the respective group is allowed to enter the lab on a specific date. This is assured by blocking the access to the lab for everyone else. This makes it possible to use a single cleaning slot per day.

For your personal safety everyone is provided at the semester start a personal safety equipment (face mask and shield). To pick it up contact the teaching personal on the TU Chat Channel. Make sure that you bring everything with you when entering the lab and that you follow the rules in place for lab usage published by TU Wien. Although the lab is cleaned daily we recommend to disinfect the equipment (Keyboard, monitor, FPGA board, oscilloscope) when you arrive (disinfect liquid in spray cans and towels will be provided) and regularly open the windows. For sensitive electronic devices (oscilloscope, FPGA board) spray limited liquid on a towel and wipe across the turned off device. Wait until all liquid is evaporated and only then turn it back on.

For each design you have to create a short presentation after you are done with your implementation. The purpose of this exercise is to prepare you for the ever increasing demand of proper selling. Being it on a conference, where you thrive to keep the attention of the audience, at work to convince your boss/coworker of your idea or for selling your product. Custom tailored presentations are a major key whereat you should consider the following guidelines:

  • The talk length is limited to 20 min.
  • Every member of the group should talk in (equally) parts. Naturally this screams for splitting the task and making separate mini-presentations. However, you can only benefit from your colleagues if you work jointly. Therefore we highly encourage collaboration instead of cooperation.
  • Since the lecture staff, which is familiar with the task description, is your audience you do not need to repeat the problem.
  • Keep a clear structure in your talk. You may want to follow the order of the subtasks in the assignments but you do not have to. For the audience grasping new stuff is easier when it is connected to things that are already known. If possible use such attachment points.
  • Design your slides properly. In this regard less is more. How much text is optimal often depends on who you ask. Some demand more to also capture people that are not listening while others propose a maximum word count of 20 per slide. Overall you should avoid full sentences, make pictures well readable and focus on the message you want to send.
  • The arguably hardest part is the talking itself. Try to speak slowly, maybe even slower than you anticipate. Making pauses is not always a bad thing but gives the audience some time to process the information just heard.
  • Try to convince the audience that your investigations are sound and your solution is appropriate. Therefore properly present your gathered data and explain them. Tell the listeners what conclusion you drew from your observations, how you tackled them and maybe present an evaluation of your solution.

Upload your slides within the given time frame to TUWEL. The actual presentation can be scheduled dynamically with the teaching staff. Even cumulating some or all of them is possible, e.g. do pick a date in January where you present everything at once. On presentation day you first give your talk remotely (the tool will be announced when you schedule your talk) and afterwards download your application to one of the FPGA boards in the lab. The teaching staff will be present in the TILab and observe the behavior live while you control the board from remote. The time frames for the three designs are:

  1. clock domain crossing: 11.11.2020 - 9.12.2020
  2. develop asynchronous logic with an HDL: 2.12.2020 - 8.1.2021
  3. STGs and asynchronous communication protocol: 16.12.2020 - 20.1.2021

The grade is accumulated in the following shares:

  • 75 % your implementations of the assignments
  • 25 % presentation of your solutions

Use the chance to provide for each design concrete feedback. This helps us to improve the lectures and is very much appreciated.