Advanced Digital Design (WS 2017)

The course focuses on advanced timing issues in digital design. The need for design methodologies is elaborated, and alternatives to the traditional synchronous design style are discussed, such as "globally asynchronous locally synchronous (GALS)" and purely asynchronous styles (bounded delay as well as delay insensitive). The scope spans from the underlying theory to practical design flow. In context with synchronous design and GALS, metastability issues are treated in much detail.

General Information about the Course

The course comprises a mix of lecture blocks, exercise blocks and labs. The latter two are concerned with discussing homeworks (results of questions/calculations and circuit designs, respectively).

The homework assignments can be downloaded below. The solutions must be provided as .pdf and uploaded to myti on the day before the respective exercise block, before 12:00 noon.


Course Dates

An introduction into scope and organization of the course will be given in the first lecture on Wednesday, October 5, 2016 at 9.00 s.t. in lecture room HS4 (Hochstetter)
Please register for the course in TISS


Regular Lectures and Exercises:

  • The regular lecture date is Wednesday  9:00 c.t. to 11:00 in lecture room HS4 (Hochstetter)
  • In addition there are extra slots for the presentation of the homeworks and lab exercises, namely on selected Tuesdays 13:00 c.t. to 15:00 in seminar room TI
    (for details see table below)


Final Exam:

  • tbd




Course Materials (continuously extended)

The lecture slides will be available below.

For the lectures on Asynchronous Logic Design the following text book is additionally recommended:

Jens Sparso and Steve Furber
Principles of Asynchronous Design -- A Systems Perspective
Kluwer Academic Publishers, 2001

For students a free .pdf version of chapters 1 - 7 of this book is available at Jens Sparso's homepage.

A very good survey on asynchronous logic can also be found in the following articles:
S.M. Nowick, M. Singh, Asynchronous Design—Part 1: Overview and Recent Advances, IEEE Design & Test, vol 32(3) and
S.M. Nowick, M. Singh, Asynchronous Design—Part 2: Systems and Methodologies , IEEE Design & Test, vol 32(3).

A very good introduction and survey of static pipelines can be found in our students' project report on CLAP. Further details about Asynchronous Pipelines are given in the survey article S.M. Nowick, M. Singh, High-Performance Asynchronous Pipelines: An Overview, IEEE Design & Test of Computers, vol 28(5), 2011

A comparison of delay-insensitive codes as well as an efficient method for building completion detectors can be found in conference papers that resulted from one of our students' projects.

For additional reading about Synchronizers the following book

David J. Kinniment and Alex Yakovlev
Synchronization and Arbitration in Digital Systems

as well as the article Ran Ginosar, Metastabilty and Synchronizers: A Tutorial, IEEE Design & Test of Computers, vol 28(5) , 2011

are recommended. A comprehensive survey on synchronizer techniques is given in the Master thesis by Robert Kutschera.




Date Topic Materials
October 5,         9:00 - 11:00 1 - Organization, The Role of Time

organization slides .ppt .pdf
lecture slides .ppt .pdf
paper on Hazards and Glitches

October 12,       9:00 - 11:00 2 - Timing Model & Synchronous Design lecture slides .ppt .pdf
paper about timing model
October 19,       9:00 - 11:00 3 - Metastability Models

lecture slides .ppt .pdf
assignments exercise 1 solution template 1
paper on MTBU equation
paper on oscillatory metastability

November 8,    13:00 - 15:00 RA - Discussion Exercise 1 solutions exercise 1
November 9,      9:00 - 11:00 3 - Metastability Measurement, Synchronizers

paper on metastability measurement w case distinction
assignments design 1
paper on metastability containment in FPGAs

November 16,    9:00 - 11:00 4 - GALS Design, Pausable Clocks

lecture slides .ppt .pdf
Master thesis Kutschera (Synchronizers)
paper on impossibility of switching a clock without metastability
paper on synchronizing a pausible clock

November 23,    9:00 - 11:00

5 - Asynchronous Design - Principles, Bundled Data

lecture slides .ppt .pdf
assignments design 2
assignments exercise 2

solution template

November 29,  13:00 - 15:00 DA - Discussion Design 1

design solutions

November 30,    9:00 - 11:00 6 - Delay Insensitive Asynchronous Design Styles

lecture slides .ppt .pdf

December 6,   13:00 - 15:00 RB - Discussion Exercise 2 solutions exercise 2
December 7,     9:00 - 11:00 7 - Asynchronous Data-flow Structures lecture slides .ppt .pdf
December 13,  13:00 - 15:00

DB - Discussion Design 2

design solutions

December 14,  9:00 - 11:00

8 - Synthesis of Control Circuits

lecture slides  .ppt .pdf
assignments exercise 3 
solution template
assignments design 3

January 11,      9:00 - 11:00 9 - Description Methods for asynchronous design

lecture slides  .ppt  .pdf

January 17,    13:00 - 15:00 RC - Discussion Exercise 3 solutions exercise 3  .pdf
January 18,      9:00 - 11:00 10 - Asynchronous Design Automation lecture slides  .ppt  .pdf
January 24,    13:00 - 15:00 DC - Discussion Design 3 design solutions
January 25,      9:00 - 11:00 11 - Asynchronous versus Synchronous  



The grading will be based on the following scheme

  • exercises (quality of submitted solutions, presentation of solution): 30%
  • labs (quality of submitted solutions, presentation of solution): 35%
  • written exam: 35%
  • extra credits can be attained through contributions to discussions during lectures, these will go on top of the above budget

For a positive grade, at least 40% of the achievable credits in each category must be reached, as well as at least 50% overall; the borderlines for the other grades will be at 62.5%, 75%, 87,5%, accordingly.



the following competences shall be conveyed:

  • practically apply the knowledge obtained from the associated lecture
  • practically apply the relevant design methods
  • correctly respect the limitations of the chosen method in a practical application


contents of the associated lecture (182.755)


Dipl.-Ing. Dr.techn. Steininger Andreas