Design and Physical Implementation of a Target ASIC for SET Experiments

Abstract - We present design aims and implementation results of a digital ASIC that is dedicated as a target for radiation experiments. Accordingly, it carries different target circuit blocks whose purpose is to study susceptibility to radiation as well as propagation of radiation effects. On-chip measurement infrastructure is mainly comprised of counters that record single event transients in various nodes of the target blocks. As it competes with the target blocks for chip area, it must be kept as small as possible, in spite of the need of being tolerant to particle hits in itself, which cannot be avoided in some types of radiation experiments. We sketch our respective solutions and present the resulting area distribution of the final ASIC layout for an industrial 65nm bulk CMOS process. We also show how we optimized the layout for the purpose of our experiments and present all relevant implementation details.