Accelerator-based Experimental Analysis and Simulation Modeling of Single-Event Transients in VLSI Circuits (EASET)

 
Funding: FWF stand-alone project
Time Frame: 01. 04. 2014 - 31. 12. 2017

Abstract

The overall aim of the project EASET is the elaboration of a more faithful but still easy to use model for the representation of single-event-transients (SETs) in analog-level (SPICE) simulation. Such a model shall form a foundation for an efficient assessment and optimization of radiation-tolerance techniques. The project methodology is to perform extensive physical-level (TCAD) simulations to thoroughly understand the charge flows induced by a radiation particle hit. These TCAD models need to be calibrated, which is a non-trivial task. Therefore, as an important part of the project, a physical ASIC prototype is designed and subjected to radiation in physical experiments to facilitate such a calibration.
EASET is a joint project between the Institute of Computer Engineering (E191) and the Institute of Institute of Electrodynamics, Microwave and Circuit Engineering (E354).

Overview

Due to the steadily decreasing feature sizes of modern VLSI circuits, which are in the nanometer range (< 100 nm) nowadays, single-event effects (SEEs) are increasingly dominating the fault rate of VLSI circuits. SEEs occur when junctions of transistors are hit by ionized particles. Such particles primarily originate in high-energy cosmic radiation, affecting a chip either directly (at high altitudes, i.e., in space and aerospace) or indirectly, via interaction with the atmosphere. The primary concern in modern VLSI circuits are transient SEEs: An ionized particle deposits charge along its track, which in turn can cause a single-event transient (SET) signal pulse (0.1-1 ns range). If a sufficiently strong SET propagates to a storage element, it can be latched, thereby producing a single-event upset (SEU).

Robust circuit design, in particular, for critical applications, hence needs models that accurately describe SETs/SEUs and are easy and efficient to use at early design stages. Such models both allow (a) to assess the radiation tolerance of different architectural designs and hardening techniques and (b) to estimate the final error rate of a circuit. The preferred method to accomplish this is simulation-based fault injection at the (analog) electrical level: Typically, a Spice model of the circuit (derived automatically from the design using technology libraries) is augmented with Spice models that simulate SET generation in critical parts of the circuit. The most commonly approach here is single-ended injection of a double-exponential current into the drain of a transistor.

Obviously, the suitability of this method for validating the effectiveness of radiation-hardening measures and predicting soft-error rates stands or falls with the availability of accurate Spice models for SET generation: If it fails to cover important scenarios, one might e.g. overlook situations where radiation-hardening fails. Unfortunately, there is evidence that standard double-exponential Spice models are susceptible to such problems, with respect to several aspects: (1) Inadequate model structure, (2) calibration of model parameters, and (3) SEEs affecting multiple transistors.

Any attempt to developing Spice models that accurately model SET generation (including the above complications) in nanometer VLSI circuits requires a combination of both (a) a detailed understanding of the physical/electrical processes involved and (b) a comprehensive experimental evaluation of SET pulses arising in real circuits. The project EASET is devoted to this purpose: It will use results from accurate analog SET measurements in carefully designed measurement ASICs under micro-beam irradiation to (i) guide the development and (ii) calibrate detailed 3D physical/hybrid TCAD simulation models. The latter is a very powerful means for researching the SET generation process and its parameters in VLSI circuits, and thus also the appropriate basis for developing and validating novel SET generation Spice models for complex nanometer VLSI circuits, which are the primary intended outcome of the project.

The measurement ASICs will include on the one hand the circuits under test, e.g. circuits based on basic combinational and sequential logic and possibly some other topologies like ring oscillators. On the other hand the ASICs will include high speed analog measurement amplifiers which must have minimum influence on the investigated circuit nodes, and they have to include high speed analog 50Ω-output drivers. Additional analog high speed multiplexers are necessary due to the large number of investigated circuit nodes. Consequently, EASET not only addresses interesting fundamental research questions, but also provides results that are relevant in practice. The required competence is ensured by running it as a joint project between the Institut für Technische Informatik and the Institute of Electrodynamics, Microwave and Circuit Engineering at TU Wien, which also includes external collaborations with radiation physics experts e.g. at the GSI in Darmstadt and the PTB in Braunschweig.

 

Collaborators

Institute of Computer Engineering

ecs.png


Vienna University of Technology
Institute of Computer Engineering
Embedded Computing Systems Group, E191-2
http://www.ecs.tuwien.ac.at

 

Andreas Steininger - Project Head

Varadan Savulimedu Veeravalli - Radiation-modeling, design of the digital radiation test circuit

Bernhard Fritz - Data transfer and digital ASIC testing

Institute of Electrodynamics, Microwave and Circuit Engineering

TU_EMCE.png

Vienna University of Technology
Electrodynamics, Microwave and Circuit Engineering
Circuit Design, E354
http://www.emce.tuwien.ac.at/en/

 

Horst Zimmermann - Co-project Head

Michael Hofbauer - 3D SET simulations, radiation experiments, data processing, evaluation

Mladen Mitrovic - Radiation test circuit design

External collaborations

Person Institution Topic/Task
Günther Dollinger SNAKE, TU Munich Micro-beam Radiation Experiments
Kay-Obbe Voss GSI Helmholtz Center, Darmstadt Micro-beam Radiation Experiments
Miloš Krstić IHP Microelectronics Frankfurt Radiation-tolerant VLSI design
Lorena Anghel TIMA Labs Grenoble Radiation effects in VLSI
Dan Alexandrescu IROC Technologies  Research collaborator
Mario Villa Atominstitut, Wien Neutron beam exposure
Václav Šimek Brno University of Technology Radiation target ASIC preparations
Erwin Deumens IMEC Sign-off of analog and digital ASIC for tape-out

 

Publications

Workshop and Conference Publications

[1] Long term on-chip monitoring of SET pulsewidths in a fully digital ASIC

Veeravalli, V.S. and Steininger, A.
22nd Austrian Workshop on Microelectronics (Austrochip), Oct, 2014

[2] Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example

Steininger, A. and Veeravalli, V.S. and Alexandrescu, D. and Costenaro, E. and Anghel, L.
32nd IEEE International Conference on Computer Design (ICCD), Oct, 2014

[3] Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum

Lorena Anghel and Varadan Savulimedu Veeravalli and Dan Alexandrescu and Andreas Steininger and Kerstin Schneider-Hornstein
IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), 2014

[4] Can we trust SPICE-Level SET Models?

V. S. Veeravalli and A. Steininger
Proceedings of the MEDIAN Workshop, 2015

[5] Reliable and Continuous Measurement of SET Pulse Widths

V. S. Veeravalli and A. Steininger
2015 Euromicro Conference on Digital System Design, Aug, 2015

[6] Study of a Delayed Single-Event Effect in the Muller C-element

V. S. Veeravalli and A. Steininger
21th IEEE European Test Symposium (ETS), May, 2016

[7] Design and Physical Implementation of a Target ASIC for SET Experiments

V. S. Veeravalli and A. Steininger
2016 Euromicro Conference on Digital System Design (DSD), 2016

[8] Dependence of inverter chain single-event cross sections on inverter spacing in 65 nm bulk CMOS technology

M. Mitrovic and M. Hofbauer and B. Goll and K. Schneider-Hornstein and R. Swoboda and B. Steindl and K. O. Voss and H. Zimmermann
2016 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2016

[9] A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study

M. Andjelkovic and M. Krstic and R. Kraemer and V. S. Veeravalli and A. Steininger
2017 IEEE 26th Asian Test Symposium (ATS), 2017

[10] Setup for an Experimental Study of Radiation Effects in 65nm CMOS

B. Fritz and A. Steininger and V. Simek and V. S. Veeravalli
2017 Euromicro Conference on Digital System Design (DSD), 2017

Journals

[1] Building reliable systems-on-chip in nanoscale technologies

A. Steininger, H. Zimmermann, A. Jantsch, M. Hofbauer, U. Schmid, K. Schweiger, and V. S. Veeravalli
e \& i Elektrotechnik und Informationstechnik, Sep, 2015

[2] A Versatile Architecture for Long-Term Monitoring of Single-Event Transient Durations

V. S. Veeravalli and A. Steininger and U. Schmid
Microprocessors and Microsystems, 2017

[3] Experimental Investigation of Single-Event Transient Waveforms Depending on Transistor Spacing and Charge Sharing in 65 nm CMOS

M. Mitrovic and M. Hofbauer and B. Goll and K. Schneider-Hornstein and R. Swoboda and B. Steindl and K. O. Voss and H. Zimmermann
IEEE Transactions on Nuclear Science, 2017

[4] A DC-to-8.5 GHz 32:1 Analog Multiplexer for On-Chip Continuous-Time Probing of Single-Event Transients in a 65-nm CMOS

M. Mitrovic and M. Hofbauer and B. Goll and K. Schneider-Hornstein and R. Swoboda and B. Steindl and K. O. Voss and H. Zimmermann
IEEE Transactions on Circuits and Systems II: Express Briefs, 2017

[5] Evidence of Pulse Quenching in AND and OR Gates by Experimental Probing of Full Single-Event Transient Waveforms

M. Mitrovic and M. Hofbauer and K. Schneider-Hornstein and B. Goll and K. O. Voss and H. Zimmermann
IEEE Transactions on Nuclear Science, Jan, 2018

[6] Experimental Investigation of the Joint Influence of Reduced Supply Voltage and Charge Sharing on Single-Event Transient Waveforms in 65-nm Triple-Well CMOS

M. Mitrovic and M. Hofbauer and K. O. Voss and H. Zimmermann
IEEE Transactions on Nuclear Science, 2018

Reports

[1] Literature Survey on SET injection models for SPICE

Veeravalli, V.S.
Department of Computer Engineering, TU Vienna, 2015

[2] Radiation Experiments in the Nuclear Reactor

Fabian Fuhrmann
TI Practical, Institute of Computer Engineering, TU Wien, Vienna, Austria, 2017

Dissertations

[1] Single Event Transients in 90 nm CMOS

M. Hofbauer
PhD Thesis, Institute of Electrodynamics, Microwaves and Circuit Engineering, TU Wien, Vienna, Austria, 2016

[2] Design of custom ASIC for radiation experiments to study single event effects

Savulimedu Veeravalli, Varadan
PhD Thesis, Institute of Computer Engineering, TU Wien, Vienna, Austria, 2017

Master Theses

[1] Operation and Verification Framework for the FRad Experimental ASIC

Bernhard Fritz
Master Thesis, Institute of Computer Engineering, TU Wien, Vienna, Austria, 2018

Posters

[1] Dependence of Inverter Chain Single-Event Cross Sections on Inverter Spacing in 65 nm Bulk CMOS Technology

M. Mitrovic, M. Hofbauer, B. Goll, K. Schneider-Hornstein, R. Swoboda, B. Steindl, K.-O. Voss, and H. Zimmermann
16th European Conference on Radiation and Its Effects on Components and Systems (RADECS), Bremen, Sep, 2016

[2] Evidence of Pulse Quenching in AND gates in 65 nm Bulk CMOS by Experimental Probing of Full Single-Event Transient Waveforms

M. Mitrovic, M. Hofbauer, K. Schneider-Hornstein, B. Goll, K.-O. Voss, and H. Zimmermann
IEEE Nuclear and Space Radiation Effects Conference (NSREC), New Orleans, Louisiana, July, 2017

[3] Experimental Investigation of the Joint Influence of Reduced Supply Voltage and Charge Sharing on Single-Event Transient Waveforms in a 65 nm Triple-Well CMOS

M. Mitrovic, M. Hofbauer, K.-O. Voss, and H. Zimmermann
17th European Conference on Radiation Effects on Components and Systems (RADECS), Geneva, Switzerland, Oct, 2017