Current Projects

Research Projects at the Embedded Computing Systems Groups

IoT4CPS: Trustworthy IoT for CPS

IoT4CPS: Trustworthy IoT for CPS

Funding: AT-FFG

Partners: TU Wien, Austrian Institut of Technology (AIT), Institute of Science and Technology (IST), AVL List GmbH, Donau Uni Krems, Infineon Technologies AG, JKU Linz, Joanneum, NOKIA Österreich, NXP, Salzburg Research, SBA Research, SCCH, Siemens AG Österreich, TTTech Computertechnik AG, TU Graz, X-Net Services GmbH

Time Frame: started 01. 12. 2017

Contact Persons: Ezio Bartocci, Muhammad Shafique

Research Team: Ezio Bartocci (project leader), Muhammad Shafique, Faiq Khalid

IoT4CPS will develop guidelines, methods and tools to enable safe and secure IoT-based applications for automated driving and for smart production. The project will address safety and security aspects in a holistic approach both along the specific value chains and the product life cycles. To ensure the outreach of the project activities and results, the relevant stakeholders will be involved throughout the project and results will be disseminated to expert groups and standardization bodies. IoT4CPS will support digitalization along the entire product lifecycle, leading to a time-to-market acceleration for connected and autonomous vehicles. IoT4CPS will provide innovative components, leading to efficiency increases for the deployment of autonomous driving functions and in smart production environments, which will be validated in a vehicle and in a smart production demonstrator.

Digital Modeling of Asynchronous Integrated Circuits

Funding: Austrian Science Fund (FWF)

Collaborators: Matthias Függer (ENS Paris-Saclay),Thomas Nowak (Université Paris-Sud), Sayan Mitra (U. Illinois at Urbana-Champaign), Laura Nenzi (U. of Trieste), Ezio Bartocci (TU Wien)

Time Frame: started 01. 07. 2019

Contact Persons: Ulrich Schmid

Research Team: Ulrich Schmid, Jürgen Maier

The project Digital Modeling of Asynchronous Integrated Circuits (DMAC) is devoted to the development of a purely digital model for asynchronous circuits, which enables accurate and fast dynamic timing analysis and is a mandatory prerequisite for any attempt on practical formal verification of such designs. The envisioned model shall be accurate and realistic (= faithful), in the sense that the behavior of circuits described in the model is exactly, i.e., within the modeling accuracy, the same as the behavior of the corresponding real circuit. In contrast to analog models, which are known to be faithful but suffer from excessive simulation times, we target continuous-time discrete-value models here, which essentially boil down to elaborate delay models for gates and/or interconnecting channels.

The project builds on our novel involution model, which considers input-to-output delays as as function of the history in the signal trace. DMAC will fully explore this avenue scientifically, by answering questions such as how to enlarge the class of circuits where the involution model and variants thereof are faithful, how to compose gates with different electrical properties, in particular, different threshold voltage levels, how to accurately model subtle delay variation originating in the Charlie effect in multi-input gates, how to parametrize and characterize the model for a given technology and given operating conditions, and how to possibly further improve the modeling coverage and accuracy. In addition, we will also make the first steps to incorporate our models into existing timing analysis and verification tools for validation purposes.

read more...

Reasoning about Knowledge in Byzantine Distributed Systems

Funding: Austrian Science Fund (FWF)

Time Frame: started 01. 07. 2020

Contact Persons: Roman Kuznets, Ulrich Schmid

Research Team: Roman Kuznets, Ulrich Schmid, Giorgio Cignarale, Krisztina Fruzsa, Hugo Rincon Galeana, Thomas Schlögl

Reasoning about fault-tolerant distributed systems, which consist of networked processors without a central control that need to achieve a common goal, is notoriously difficult due to the many sources of uncertainty: varying execution speeds, unpredictable transmission delays, and partial failures make it difficult for a processor to establish local knowledge sufficient to safely perform required actions.

The goal of the proposed project is to incorporate arbitrarily misbehaving agents into an epistemic reasoning framework and to supplement the standard Kripke semantics with a suitable topological semantics for distributed systems, while exploiting, and being informed by, the success of Dynamic Epistemic Logic in capturing the dynamics of knowledge evolution in modal logic.

read more...