Past Projects

Past Research Projects at the Embedded Computing Systems Groups

SCDL - Seamless Campus: Distance Labs

Funding: BMVIT, FIT-IT Embedded Systems, FFG, Eutema

Time Frame: started 01. 08. 2004

The Seamless Campus: Distance Labs project (SCDL) is devoted to introduce distance labs in our main hardware-centric courses. The project focuses on two concepts: remote-controlled hardware and carry-out equipment. Another major part of the project is the setup of a surrounding environment to efficiently hold courses in distance education.

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DARTS - Distributed Algorithms for Robust Tick Synchronization

DARTS - Distributed Algorithms for Robust Tick Synchronization

Funding: BMVIT, FIT-IT, FFG, EUTEMA

Partners: Austrian Aerospace GmbH

Time Frame: started 01. 10. 2005

Contact Persons: Andreas Steininger

Research Team: Ulrich Schmid, Andreas Steininger

The FIT-IT project DARTS — Distributed Algorithms for Robust Tick Synchronization is dedicated to the development of a novel method to provide synchronous systems with a robust and fault-tolerant clocking methodology to overcome the problems and limitations of currently used approaches.

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DECOS

DECOS

Funding: Sixth EU Framework Programme for Research and Technological Development (FP6)

Time Frame: started 01. 07. 2004

Contact Persons: Hermann Kopetz

Research Team: Hermann Kopetz

DECOS - Dependable Embedded Components and Systems is an Integrated Project within the Sixth EU Framework Programme for Research and Technological Development (FP6) and has a duration of 36 months.

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ARTIST2

ARTIST2

Funding: Sixth EU Framework Programme for Research and Technological Development (FP6)

Time Frame: started 01. 09. 2004

Contact Persons: Hermann Kopetz

Research Team: Peter Puschner, Hermann Kopetz

ARTIST2 is an FP6 Network of Excellence on Embedded Systems Design and has a duration of 48 months.

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Te-Des

Te-Des

Funding: FIT-IT, BMVIT

Time Frame: started 01. 03. 2005

Contact Persons: Peter Puschner

Research Team: Peter Puschner

The Te-Des project is supported by FIT-IT, an Austrian research programme initiatiated by the Austrian Federal Ministry of Transport, Innovation, and Technology (BMVIT) and has a duration of 24 months.

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TT-Ethernet

Funding: FIT-IT, BMVIT

Time Frame: started 01. 03. 2004

Contact Persons: Hermann Kopetz

Research Team: Hermann Kopetz

The TT-Ethernet project is supported by FIT-IT, an Austrian research programme initiatiated by the Austrian Federal Ministry of Transport, Innovation, and Technology (BMVIT) and has a duration of 34 months.

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TTCAR

TTCAR

Funding: Austrian Science Fund (FWF)

Time Frame: started 01. 09. 2005

The TTCAR (Time-triggered communication architecture for robotic systems) project, dealing with basic research, is funded by the Austrian Science Fund (FWF) and has a duration of 36 months.

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THETA

THETA

Funding: FWF

Partners: INRIA Rocquencourt, Projet NOVALTIS, France

Time Frame: started 08. 12. 2004

Contact Persons: Ulrich Schmid

Research Team: Ulrich Schmid

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ExTract

ExTract

Funding: BMVIT, FIT-IT Embedded Systems, FFG, Eutema

Time Frame: started 01. 10. 2005

Contact Persons: Andreas Steininger

Research Team: Andreas Steininger

The FIT-IT project ExTraCT — Exploiting Synchrony for Transparent Communication Services Testing — is dedicated to the concept and development of a novel method to enable the transparent testing of time-triggered communication protocols.

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COSTA

COSTA

Funding: Austrian Science Fund (FWF)

Partners: Real-Time Systems Group, Vienna University of Technology
Compilers and Languages Group, Vienna University of Technology

Time Frame: started 01. 07. 2006

Research Team: Peter Puschner

The COSTA (Compiler-Support for Timing Analysis) project, dealing with basic research, is funded by the Austrian Science Fund (FWF) and has a duration of 36 months.

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SPAWN

Funding: FWF

Time Frame: started 01. 09. 2005

The project SPAWN shall develop and analyze failure models, protocols and algorithms for basic fault-tolerant distributed computing problems like consensus and clock synchronization that run directly atop of sparse networks.

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TT-SoC

TT-SoC

Funding: FIT-IT (Research Programme initiatiated by the Austrian Federal Ministry of Transport, Innovation, and Technology (BMVIT))

Partners: TU Vienna; TTTech Computertechnik AG

Time Frame: started 01. 03. 2007

Contact Persons: Hermann Kopetz

Research Team: Hermann Kopetz

It is the objective of the TT-Soc (Time-Triggered System-on-a-Chip Architecture) research project to lay the foundation for a next-generation embedded system architecture that provides a predictable integrated execution environment for the component-based design of many different types of embedded applications.

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FORTAS

FORTAS

Funding: Austrian Science Fund (FWF)

Time Frame: started 01. 01. 2007

The FORTAS project, dealing with basic research in the field of execution time analysis of embedded software, is funded by the Austrian Science Fund (FWF) and has a duration of 36 months.

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GENESYS

GENESYS

Funding: EC

Time Frame: started 01. 01. 2008

Research Team: Hermann Kopetz

GENESYS (GENeric Embedded System Platform) is an European research project funded by the European Community's Seventh Framework Programme (FP7/2007-2013) under the grant agreement number FP7-213322. The GENESYS consortium consists of 23 project partners from 11 different European countries and is coordinated by TU Vienna.

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JEOPARD

Funding: EC

Time Frame: started 01. 01. 2008

JEOPARD (Java Environment for Parallel Realtime Development) is an FP7 collaborative project. The JEOPARD consortium consists of 10 project partners, among them TU Vienna, and is coordinated by X/OPEN.

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ARTIST Design

Funding: EC FP7

Time Frame: started 01. 01. 2008

Contact Persons: Peter Puschner

Research Team: Peter Puschner

The FP7 Network of Excellence "ArtistDesign – Design for Embedded Systems" has 31 project partners and is coordinated by UNIVERSITE JOSEPH FOURIER.

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SECCO

SECCO

Funding: FWF, WIEN, Österreich

Time Frame: started 01. 07. 2008

The SECCO (Sustaining Entire Code-Coverage on Code Optimization) project is concerned with software testing, focusing in particular on the support of gray-box testing, and is funded by the Austrian Science Fund (FWF) with a duration of 24 months.

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PSRTS

Funding: FWF

Time Frame: started 26. 02. 2008

Contact Persons: Ulrich Schmid

Research Team: Ulrich Schmid

The project "Partially Synchronous Distributed Real-Time Systems" (PSRTS) is devoted to the development of a sound scientific basis for fault-tolerant distributed hard real-time systems with a high degree of concurrency and, hence, relaxed synchrony-by-design. Its purpose is to revise/adapt/extend existing approaches in order to add a proper real-time systems perspective to the theory of distributed algorithms.

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CLIC

CLIC

Funding: FIT-IT (Research Programme initiatiated by the Austrian Federal Ministry of Transport, Innovation, and Technology (BMVIT))

Partners: TTTech Computertechnik AG; Alpen-Adria Universität Klagenfurt,
Institut für Vernetzte und Eingebettete Systeme; Technische Universität Wien, Instituts für Automatisierungs- und Regelungstechnik; Technische Universität Wien,
Institut für Technische Informatik;

Time Frame: started 01. 01. 2009

The objective of the CLIC (Closed-Loop Integration of Cognition, Communication and Control) project is to integrate real-time image analysis, adaptive motion control, and synchronous communication between the imaging and control subsystems.

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FATAL

Funding: FWF

Partners: Institut für Elektrische Mess- und Schaltungstechnik (Horst Zimmermann)

Time Frame: started 01. 10. 2009

Contact Persons: Ulrich Schmid, Andreas Steininger

Research Team: Ulrich Schmid, Andreas Steininger

The aim of the FATAL project is the development of the mathematical/formal foundations of a framework for the hierarchical modeling and analysis of fault-tolerant asynchronous VLSI circuits, using fault-tolerant distributed algorithms knowledge in conjunction with the experimental assessment of both radiation-induced failures and metastability in modern VLSI technology. FATAL is a joint project between the Institut für Technische Informatik and the Institut für Elektrische Mess- und Schaltungstechnik at TU Wien.

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INDEXYS

INDEXYS

Funding: ARTEMIS-JU; FFG

Partners: TTTech Computertechnik AG (Coordinator); Thales Rail Signalling Solutions GmbH; Audi AG; EADS Deutschland GmbH; Technical University of Darmstadt; Technical University of Kaiserslautern; OptXware Research and Development Ltd.; Delft University of Technology; NXP Semiconductors Netherlands B.V.; Vienna University of Technology;

Time Frame: started 01. 04. 2009

Contact Persons: Hermann Kopetz

Research Team: Roman Obermaisser, Hermann Kopetz

INDEXYS - INDustrial EXploitation of the genesYS cross-domain architecture - is a cross-industry research & development project consisting of 10 organisations including Industries, SMEs and Universities from European 4 countries (Austria, Germany, Hungary, The Netherlands). The project is co-funded by the ARTEMIS Programme (Topic “SP5 Computing Environments for Embedded Systems”).

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ACROSS

ACROSS

Funding: ARTEMIS-JU; FFG

Partners: Vienna University of Technology (Coordinator); AVL List GmbH; EADS Innovation Works; TTTech Computertechnik AG; Thales S.A.; SELEX Sistemi Integrati S.p.A.; Danube Mobile Communications Engineering GmbH & Co KG; Siemens AG Österreich; EADS France; ForTISS GmbH; Université Joseph Fourier Grenoble 1 /Verimag; EADS Defense Electronics; SYSGO AG; Lauterbach; Thales Communications S.A.; PrismTech.

Time Frame: started 01. 04. 2010

ACROSS (ARTEMIS CROSS-Domain Architecture) is a research project that aims to develop and implement an ARTEMIS cross-domain reference architecture for embedded systems based on the architecture blueprint developed in the European FP7 project GENESYS.

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ARCADIA

Funding: EC

Time Frame: started 01. 11. 2009

Contact Persons: Hermann Kopetz

Research Team: Hermann Kopetz

The ARCADIA (Aligning ResearCh AgenDas In ARTEMIS) project main objective is to have better and effective coordination of the efforts in order to optimize the use of the resources, and to contribute in to the advance of an ERA for the Embedded System field to strengthening Europe´s future growth, competitiveness and sustainable development.

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MultiPARTES - Multi-cores Partitioning for Trusted Embedded Systems

MultiPARTES - Multi-cores Partitioning for Trusted Embedded Systems

Funding: EU FP7

Partners: Ikerkan-IK4 (Spain), Universitat Politecnica de Valencia (Spain), TU Wien (Austria), Universidad Politecnica de Madrid (Spain), TRIALOG (France), Fent Innovative Software Solutions (Spain), TELETEL (Greece), Visual Tools (Spain), ALSTOM Wind (Spain)

Time Frame: started 01. 09. 2011

Contact Persons: Peter Puschner

Research Team: Peter Puschner, Haris Isakovic

This project aims at developing tools and solution based on mixed criticality virtualization systems for multicore platforms. The starting point for the virtualization support is XtratuM, a cost-effective open source hypervisor developed specifically for real-time embedded systems by one of the project participants (UPVLC) - a hypervisor that is being increasingly used by the aerospace industry. Based on this approach, MultiPARTES will offer a rapid and cost-effective development support on dependable real-time embedded systems enabling critical and non critical applications to run on the same hardware platform. To achieve this goal we will develop an innovative multicore-platform virtualization based on XtratuM. We will devise a methodology permitting the partitioning of multicore systems, thereby speeding up the development and production of mixed-criticality applications based on the partitioning. We will demostrate these open virtualization solutions on COST hardware platforms and on enhanced heterogeneous multicore hardware platforms to show the increase of time and space isolation, overcoming some of the COTS hardware limitations. The results will be evaluated in case studies in three application sectors: wind power, video surveillance and aerospace.

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T-CREST - Time-Predictable Multi-Core Architecture for Embedded Systems

T-CREST - Time-Predictable Multi-Core Architecture for Embedded Systems

Funding: EU FP7

Partners: Technical University of Denmark (Denmark), AbsInt Angewandte Informatik (Germany), GMV (Portugal), Intecs (Italy), University of York (United Kingdom), Technical University of Eindhoven (Netherlands), Vienna University of Technology (Austria), The Open Group (United Kingdom)

Time Frame: started 01. 09. 2011

Contact Persons: Peter Puschner

Research Team: Peter Puschner, Stefan Hepp, Benedikt Huber, Univ.Prof. Jens Knoop

The T-CREST project is developing a time-predictable system that will simplify the safety argument with respect to maximum execution time while striving to double performance for 4 cores and to be 4 times faster for 16 cores than a standard processor of the same technology (e.g. FPGA). The ultimate goal of the T-CREST system will be to lower costs for safety relevant applications, reducing system complexity and at the same time achieving faster time-predictable execution.

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VeTeSS

VeTeSS

Funding: ARTEMIS-JU; FFG

Partners: Infineon Technologies UK Ltd, UK (Coordinator); Infineon Technologies AG, Germany; Infineon Technologies Austria AG, Austria; Volvo Technology AB, Sweden; SP Sveriges Tekniska Forskningsinstitut AB, Sweden; Centro Ricerche Fiat SCPA, Italy; AVL List GmbH, Austria; Technische Universitaet Wien, Austria; NXP Semiconductors Netherlands BV, Netherlands; Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V., Germany; e-AAM Driveline Systems AB, Sweden; Politecnico di Torino, Italy; IKV++ Technologies AG, Germany; SpringSoft SAS, France; TWT GmbH Science & Innovation, Germany; The University Of Oxford, UK; Barcelona Supercomputing Center - Centro Nacional de Supercomputacion, Spain; exida.com Excellence in Dependable Automation GmbH, Germany; QRTECH AB, Sweden; Rapita Systems Ltd, UK; Catena DSP, Austria; Fico-Triad SA, Spain; Catena Holding BV, Netherlands; Virtual Vehicle Competence Center, Austria;

Time Frame: started 01. 05. 2012

VeTeSS (Verification and Testing to Support Functional Safety Standards) is an ARTEMIS project to develop standardized tools and methods for the verification of safety properties, particularly for generic components and subsystems used in safety-relevant embedded systems. The project will concentrate on the strategically important automotive market.

For further information please visit the project website http://www.vetess.eu.

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AMADEOS

AMADEOS

Funding: EU-FP7

Partners: Università degli Studi di Firenze (coordinator), Vienna University of Technology, University of Grenoble I, ResilTech srl, Thales Netherlands B.V., European Network for Cyber Security

Time Frame: started 01. 10. 2013

Research Team: Hermann Kopetz

The objective of this research project is to bring time awareness and evolution into the design of System-of-Systems (SoS), to establish a sound conceptual model, a generic architectural framework and a design methodology, supported by some prototype tools, for the modeling, development and evolution of time-sensitive SoSes with possible emergent behaviors. Special emphasis is placed on evolution, emergence, dependability (e.g. safety, availability) and security, considering embedded devices and the cloud as the execution platform. The concept of evolution will be addressed from two complementary perspectives, considering both long-term evolution and short-term unexpected changes (e.g., failures) in the constituent systems. The project starts with a study of fielded industrial SoSs, where the handling of time and the evolution aspects will be in the center of the analysis, in the domains of disaster management, transport, and smart grid applications. The following development of the conceptual model, the architectural framework, the design methodology and some extensions to UML-based tools will form the core of the project work. In place of the traditional guarantees that were the target for more closed and static systems, the architectural framework will be based on the concept of guaranteed best adaptation under the given constraints, sometimes just monitoring how the environment evolves, and influencing how the SoS takes mitigating actions. The viability of the framework will be validated on a case study of a CPS, a small smart grid application, where guaranteed responsiveness, evolution, dependability and security are essential requirements. The research is based on the in-depth experience of some of the key researchers of the consortium in the fields of architecture design, real-time systems, dependability, security and the development of large systems-of-systems in such diverse domains as disaster management, the transport sector, and energy distribution.

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EMC² - Embedded Multi-Core systems for Mixed Criticality applications in dynamic and changeable real-time environments

EMC² - Embedded Multi-Core systems for Mixed Criticality applications in dynamic and changeable real-time environments

Funding: EU-ARTEMIS-JU, AT-FFG

Partners: The EMC² project consortium is made up of leading European RTOs and university institutes, a substantial number of specialized SMEs in various fields, major semiconductor manufacturer, specialized hardware and software providers and system providers from various application fields. For a list of the 99 partners see the project's website.

Time Frame: started 01. 04. 2014

Contact Persons: Radu Grosu, Haris Isakovic

Research Team: Radu Grosu, Haris Isakovic

Embedded systems are the key innovation driver to improve almost all mechatronic products with cheaper and even new functionalities. They support today’s information society as inter-system communication enabler. A major industrial challenge arises from the need to face cost efficient integration of different applications with different levels of safety and security on a single computing platform in an open context. EMC² finds solutions for dynamic adaptability in open systems, provides handling of mixed criticality applications under real-time conditions, scalability and utmost flexibility, full scale deployment and management of integrated tool chains, through the entire lifecycle. The objective of EMC² is to establish Multi-Core technology in all relevant Embedded Systems domains. In particular, it should support the emerging Cyber-Physical-Systems technology.

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CMACS - Computational Modeling and Analysis for Complex Systems

CMACS - Computational Modeling and Analysis for Complex Systems

Funding: USA-NSF-Expeditions

Partners: Carnegie Mellon University, Cornell University, Lehman College, University of Maryland, Stony Brook University, New York University, University of Pittsburgh, NASA

Time Frame: started 01. 01. 2014

Contact Persons: Radu Grosu

Research Team: Radu Grosu, Ezio Bartocci, Edmund M. Clarke, Scott A. Smolka

The CMACS project is focused on far-reaching and transformative research into techniques based on Model Checking and Abstract Interpretation (MCAI) for analyzing the behavior of complex embedded and dynamical systems. Model Checking and Abstract Interpretation have a 30-year record of success at verifying properties of the behavior of discrete systems automatically. The techniques have been fruitfully used, both independently and in combination, to establish properties of systems containing thousands of variables and inputs and several 100,000’s of lines of code (for example, the Airbus 380’s flight control software), and to detect subtle bugs in a variety of hardware and software applications, ranging from microprocessor designs and communication protocols to railway-switching systems and satellite-control software. The purpose of this project is to extend the MCAI paradigm to reasoning about the behavior of models of physical systems that include continuous and stochastic behavior, such as those found in biological and embedded-control areas. Specific research is being undertaken in model discovery / system identification for stochastic and nonlinear hybrid systems; methods for generating sound model abstractions to simplify the reasoning process; and next-generation algorithms for analyzing the behavior of these models. Challenge problems in the area of pancreatic-cancer modeling, atrial-fibrillation detection, distributed automotive control, and aerospace control software are being used as technology drivers and testbeds for the results obtained in the course of the project.

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HARMONIA - Hardware Monitoring for Automotive

HARMONIA - Hardware Monitoring for Automotive

Funding: AT-FFG

Partners: AT-Infineon, AT-AIT, AT-TU Wien

Time Frame: started 01. 09. 2014

Research Team: Ezio Bartocci, Radu Grosu

HARMONIA will provide a framework for assertion-based monitoring of automotive systems-of-systems with mixed criticality. It will enable a uniform way to reason about both safety-critical correctness and non-critical robustness properties of such systems. Observers embedded on FPGA hardware will be generated from assertions, and used for monitoring automotive designs emulated on hardware. The project outcome will improve the competitiveness of the automotive application oriented nano and microelectronics industry by reducing verification time and cost in the design process.

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SemI40 - Power Semiconductor and Electronics Manufacturing 4.0: Machine Learning over Big Data at Infineon

SemI40 - Power Semiconductor and Electronics Manufacturing 4.0: Machine Learning over Big Data at Infineon

Funding: EU-Artemis-ECSEL

Time Frame: started 01. 05. 2016

Contact Persons: Elahe Ghalebi, Radu Grosu, Hamidreza Mahyar

Research Team: Elahe Ghalebi, Anja Zernig, Olivia Bluder, Andre Kästner, Radu Grosu, Hamidreza Mahyar

SemI40 will focus on “smart production” and “cyber-physical production systems” and is one of the largest Industry 4.0 projects in Europe. Industry 4.0 also known as Cyber-Physical Production Systems are systems where sensors and actuators are combined with communication and computation in order to achieve the optimal control of physical production processes. Infineon, one of the world leaders in mixed-signal chip production, has recently embarked in a very innovative and daring project: The complete automation of one of its Villach’s production sites. This automation involves the sensing, processing, and storing of huge amounts of measurement-data related to the processes involved in their chip production. While the semiconductor fabs are currently measured and statistically analyzed after each process, there is no correlation among these measurements so far. Since such a correlation is arguably impossible to derive from first principles in physics and chemistry, we propose in this project to use machine-learning and big-data techniques to automatically learn such correlations. These correlations will be thereafter used to predict anomalies, to diagnose the processes and machines responsible for a failed fab, and to eventually control these processes for optimal fabrication.

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ICT COST Action IC1402 on Runtime Verification beyond Monitoring (ARVI)

ICT COST Action IC1402 on Runtime Verification beyond Monitoring (ARVI)

Funding: EU-Horizon 2020, EU-COST

Partners: Lübeck University (coordinator), TU Wien, Austrian Institute of Technology, Brno University of Technology, Charles University in Prague, Aalborg University, Institute of Cybernetics at TUT, Université Joseph Fourier, Ss. Cyril and Methodius University in Skopje, Universität des Saarlandes, FireEye, National Technical University of Athens, TEI of Ionian Islands, University of Iceland, Reykjavík University, Athlone Institute of Technology, Trinity College Dublin, The Academic College Tel-Aviv, Bar Ilan University, Univeristy of Milano Bicocca, Univeristy of Turin, Kaunas university of Technology, University of Luxembourg, Luxembourg Institute of Science and Technology, University of Malta, University of Groningen, University of Twente, Bergen University College, University of Oslo, Univeristy of Lisbon, NOVA University of Lisbon - FCT, University of Novi Sad, IMDEA Software Institute Universidad Carlos III de Madrid, University of Gothenburg, Universita della Svizzera Italiana, University of Manchester, University of Tartu, Fraunhofer SIT, LION Smart GmbH, University of Bologna, University of Coimbra, Chalmers University of Technology

Time Frame: started 17. 12. 2014

Contact Persons: Ezio Bartocci, Radu Grosu

Research Team: Ezio Bartocci, Radu Grosu

Project description: Runtime verification (RV) is a computing analysis paradigm based on observing a system at runtime to check its expected behavior. RV has emerged in recent years as a practical application of formal verification, and a less ad-hoc approach to conventional testing by building monitors from formal specifications. There is a great potential applicability of RV beyond software reliability, if one allows monitors to interact back with the observed system, and generalizes to new domains beyond computers programs (like hardware, devices, cloud computing and even human centric systems). Given the European leadership in computer based industries, novel applications of RV to these areas can have an enormous impact in terms of the new class of designs enabled and their reliability and cost effectiveness. This Action aims to build expertise by putting together active researchers in different aspects of runtime verification, and meeting with experts from potential application disciplines. The main goal is to overcome the fragmentation of RV research by (1) the design of common input formats for tool cooperation and comparison; (2) the evaluation of different tools, building a growing sets benchmarks and running tool competitions; and (3) by designing a road-map and grand challenges extracted from application domains.

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CPPS-DC: Doctoral College on Cyber-Physical Production Systems

CPPS-DC: Doctoral College on Cyber-Physical Production Systems

Funding: AT-TU Wien

Time Frame: started 01. 03. 2015

Contact Persons: Radu Grosu

Research Team: Radu Grosu, Ezio Bartocci, Horst Zimmermann, Friedrich Bleicher, Burkhard Kittl, Schahram Dustdar, Stefan Schulte, Stefan Biffl, Wilfried Sihn, Wolfgang Kastner, Marta Sabou, Gerti Kappel, Detlef Gerhard, Tanja Zseby, Manuel Wimmer

The support of complex industrial processes by according ICT technologies is a foundation of what is often called the next industrial revolution or "Industrie 4.0" and is therefore estimated to be a crucial research question in this field. Not surprisingly, this need has also been recognized by national and European policy makers. The topic is prominently regarded in funding schemes like the "Factories of the Future" programme of the European Union, the US Advanced Manufacturing iniative as well as major national programmes like "Produktion der Zukunft" (FFG). Also, the subject of "Industrie 4.0" has recently been established at TU Wien as an important interdisciplinary research initiative "TUWin4.0" and is the major development direction of the TU Wien Learning and Innovation Factory (LIF).

The Doctoral College "Cyber-Physical Production Systems" aims at further positioning TU Wien with TUWin4.0 as the leading research institute in Austria in this domain and to help to position the university as one of the highest ranked European research institutes in this highly relevant area. For this, the CPPS consortium brings together experts from the fields of mechanical and industrial engineering, management sciences, computer science, informatics, electrical engineering, and information technology. The goal of this interdisciplinary Doctoral College – grounded within TUWin4.0 – is to establish research collaborations among the next generation of researchers and to utilize synergies based on the different methods, approaches, and knowledge from these fields.

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MODESEC - Model-based Design of Secure Cyber-Physical Systems

MODESEC - Model-based Design of Secure Cyber-Physical Systems

Funding: EU-FP7, EU-REA

Partners: Edward A. Lee

Time Frame: started 01. 06. 2013

Contact Persons: Radu Grosu

Research Team: Radu Grosu, Edward A. Lee

The overall objective of the MODESEC project is to research the interaction between modelling and security in the context of Cyber-Physical Systems. The first step towards this goal is to develop and implement a development method for secure cyber physical systems. Our innovation is to investigate on how to use models to gain insights about a system’s security. The proposed approach strives to support CPS engineers that were not trained in cyber security to implement security. This will be achieved by integrating the secure design of a CPS in the model-based design approach to design a CPS. Model-based design tools are familiar to engineers working in many different domains. Thus, our approach enables these engineers to build more secure products by lowering the entry barriers to implement cyber security mechanisms. The second step investigates on the potential use of these models within a CPS, e.g., to detect attacks. Continuously comparing the operation of a CPS to a reference model of its intended behavior facilitates the recognition of attacks not only in the cyber, but also in the physical domain.

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ICT COST Action IC1405 on Reversible Computation - Extending Horizons of Computing

ICT COST Action IC1405 on Reversible Computation - Extending Horizons of Computing

Funding: EU-Horizon 2020, EU-COST

Partners: TU Wien, Universiteit Gent, University of Cyprus, University of Southern Denmark, Datalogisk Institut – Københavns Universitet, University of Turku, CNRS, INRIA, Karlsruhe Institute of Technology, University of Bremen, National Technical University of Athens, Reykjavik University, Trinity College Dublin, University of Bologna, IMT Institute for Advanced Studies Lucca, Eindhoven University of Technology, University of Oslo, University of Lodz, Warsaw University of Technology, Universidade do Minho, Romanian Academy, Ovidius University of Constanta, University of Nis, University of Novi Sad, University of Maribor, "Jožef Stefan" Institute, European Centre for Soft Computing, Halmstad University, Imperial College, University of Copenhagen, University of Turku, Universität Giessen, Waterford Institute of Technology, University of Camerino, University Politehnica Timisoara, Universitat Politecnica de Valencia, Middlesex University, Université Djillali Liabes

Time Frame: started 30. 04. 2015

Contact Persons: Ezio Bartocci, Radu Grosu

Research Team: Ezio Bartocci, Radu Grosu

Reversible computation is an emerging paradigm that extends the standard forwards-only mode of computation with the ability to execute in reverse, so that computation can run backwards as naturally as it can go forwards. It aims to deliver novel computing devices and software, and to enhance traditional systems by equipping them with reversibility. The potential benefits include the design of revolutionary reversible logic gates and circuits - leading to low-power computing and innovative hardware for green ICT, and new conceptual frameworks, language abstractions and software tools for reliable and recovery oriented distributed systems. Landauer's Principle, a theoretical explanation why a significant proportion of electrical power consumed by current forwards-only computers is lost in the form of heat, and why making computation reversible is necessary and beneficial, has only been shown empirically in 2012. Hence now is the right time to launch a COST Action on reversible computation. The Action will establish the first European (and the world first) network of excellence to coordinate research on reversible computation. Many fundamental challenges cannot be solved currently by partitioned and uncoordinated research, so a collaborative effort of European expertise with an industrial participation, as proposed by this Action, is the most logical and efficient way to proceed.

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CPS Transatlantic Summit

CPS Transatlantic Summit

Funding: EU-Horizon 2020

Partners: TU Wien, Fortiss GMBH (Coordinator), Aalborg University, OFFIS e.V., Universite Joseph Fourier Grenoble 1

Associate Partners: Vanderbilt University, Nashville, University of California, Berkeley, University of Maryland at College Park, University of Pennsylvania, Carnegie-Mellon University, Pittsburgh, IST Austria, Vienna, Thales, Grenoble

Time Frame: started 01. 02. 2015

Contact Persons: Radu Grosu

Research Team: Radu Grosu, Saddek Bensalem, John Baras, Werner Damm, Sanjoy Baruah, Manfred Broy, Bernhard Schätz, Alberto Sangiovelli-Vincentelli, Laïla Gide, Eric Debes, Insup Lee, Joseph Sifakis, Tom Henzinger, Bruce H. Krogh, George Pappas, Kim G. Larsen, Harald Ruess, Janos Sztipanovits

Cyber-physical systems (CPS) are a core enabling technology for securing economic leadership in embedded systems and ICT, having an enormous social and economic importance, and making decisive contributions to societal challenges. The EU and the US face common challenges to push forward the limits of the science for engineering Cyber-Physical Systems (CPS), creating a favorable environment for strategic and pre-competitive collaboration.

Transatlantic CPS Summit is an ambitious 18-month support action with the goal of facilitating and creating an enduring and sustainable collaboration campaign on CPS research and development between Europe and the US. The project achieves its overall aim by means of:

  1. Identifying and evaluating possible R&D cooperations between Europe and the US;
  2. Investigating and promoting implementation of opportunities for cooperation;
  3. Preparing a roadmap for R&D cooperation on CPS engineering between the EU and US together with recommendations for actions;
  4. Presenting final results to interested stakeholders (e.g. public bodies, industry, academic researchers) on both sides of the Atlantic.

To achieve the above, the project mobilises an outstanding multidisciplinary consortium of 7 EU partners and 5 US partners and brings together recognized CPS researchers across the EU and the US in a series of CPS Summit Workshops.

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Wearable Eye Tracking

Wearable Eye Tracking

Funding: AT-viewpointsystem GmbH

Time Frame: started 01. 07. 2013

Contact Persons: Radu Grosu

Research Team: Radu Grosu

The subject of this project is to enhance an existing eye tracking system into a wearable device fitted into a spectacle frame. The purpose of this system is to compute the direction of an individual’s gaze by monitoring the eyes with miniature camera modules. By tracking the position of the pupil over time, the viewing direction can be recorded and visualized. This information is of great value in several contexts. Road safety investigations take advantage of accurate eye trackers for analyzing the cause of accidents by examining how drivers react in stress situations. The viewing direction also provides a first-hand indication of an individual’s behavioral patterns when perceiving commercial advertisements. Eye trackers further promise new ways of seamless human-machine interaction for people with disabilities. Finally, a completely mobile solution encourages the adoption of new applications. Currently available solutions for tracking eye movements are stationary or not suitable for mobile operation due to their sub prime ergonometry or overwhelming size. Building upon an existing set of eye tracking algorithms, a hardware and software architecture is proposed to work towards a lightweight but powerful eye tracking solution which is novel in its size and ergonometry. Resolving the constraint on physical size while providing a sophisticated computational platform for image processing is the key challenge of this work.

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National Research Network RiSE/SHiNE (PP 12)

National Research Network RiSE/SHiNE (PP 12)

Funding: AT-FWF

Partners: Graz University of Technology (coordinator), Vienna University of Technology, Institute of Science and Technology Austria, Johannes Kepler University Linz, University of Salzburg.

Time Frame: started 01. 03. 2015

Contact Persons: Ezio Bartocci, Radu Grosu

Research Team: Ezio Bartocci, Radu Grosu, Christoph Kirsch, Krishnendu Chatterjee, Roderick Bloem, Armin Biere, Thomas A. Henzinger, Uwe Egly, Ulrich Schmid, Laura Kovács, Florian Zuleger, Ana Sokolova, Helmut Veith, Martina Seidl, Georg Weissenbacher

RiSE pursues the long term vision of a hardware/software system design process supported by automatic formal methods based on model checking, decision procedures, and game theory. Simultaneously, the National Research Network has the strategic goal to establish and strengthen Austria as an international hot spot in this research area. In the first three years of the 4-year funding period (Period I), we have made important steps towards both the scientific and the strategic goal. A key lesson from Period I was that non-functional aspects of system quality and correctness are critical, hard to achieve manually, and highly amenable to rigorous reasoning. We view the second period of RiSE 2015–2019 as an opportunity to position Computer Aided Verification closer to other fields of computer science which address non-functional aspects in a rigorous manner. In Period II, nine Project Part Leaders and six (mostly) junior Task Leaders will build upon the foundations established in the first years. The new Tasks that we propose either derive from a cross cutting “collaboration topic” of Period I or are new topics introduced by the recently hired faculty. All Tasks will be jointly investigated by two PIs. While the Research Clusters of Period I reflected the individual expertise of the PIs, we will now organize our Tasks along intersecting Research Lines. Each Research Line of Period II will address a non-functional aspect such as concurrency, probabilistic behavior, reliability, and quantitative measures (timing and resource consumption). This focus reflects a broader understanding of correctness beyond the Boolean notion of functional correctness that was central in Period I. Thus, our thrust will go beyond verification of functional specifications to computer aided design of programs that fulfill both functional and non-functional properties. We have therefore subtitled the second funding Period Systematic Methods in Systems Engineering, or SHiNE.

SHiNE project part PP12: Probabilistic Analysis of Distributed Systems. Modern distributed systems such as cyber-physical systems (CPS) embed sensing, computation, actuation, and communication within various physical substrata, resulting into heterogeneous, open, systems of systems. CPS examples include smart factories, smart transportation, and smart health-care. Openness (entities can join/leave the system), unpredictability (the environment is partially known), and distribution (interactions may propagate in space-time) are serious obstacles in the accurate prediction of the (emergent) behavior of CPS. In general, the exponential explosion of the CPS state space renders exhaustive state-space-exploration techniques, such as classical model checking, intractable. Approximate prediction techniques, such as statistical model checking (SMC) have therefore gained popularity in the past several years. A serious {\em obstacle} in the application of approximate techniques is their poor performance in predicting properties which represent rare~events. In such cases, the number of samples required to attain a high confidence ratio and a low error margin explodes. Two sequential Monte-Carlo techniques, importance splitting (ISpl) and importance sampling (ISam), originally developed in the statistical-physics community, hold the promise to overcome this obstacle. The main idea of the proposed work is therefore to combine Importance Sampling and Importance Splitting within a coherent and unified, control-theoretic framework}, yielding a novel and general class of SMC algorithms.

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ICT COST Action IC1202: Timing Analysis on Code Level (TACLe)

ICT COST Action IC1202: Timing Analysis on Code Level (TACLe)

Funding: EU-Horizon 2020, EU-COST

Partners: Austria, Belgium, Denmark, Finland, France, fYR Macedonia, Germany, Greece, Hungary, Ireland, Italy, Lithuania, Luxembourg, Netherlands, Norway, Portugal, Serbia, Spain, Sweden, United Kingdom

Time Frame: started 07. 11. 2012

Contact Persons: Peter Puschner

Research Team: Peter Puschner

The goal of this EU COST Action is to gather the forces of the timing-analysis community and the related communities in model checking, type interference, computer architectures and compilers in order to develop industrial-strength code-level timing analysis techniques for future-generation embedded systems.

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ARRIVE - Adaptive Runtime Verification and Recovery for Mission-Critical Software

ARRIVE - Adaptive Runtime Verification and Recovery for Mission-Critical Software

Funding: USA-AFOSR

Collaborators: Stony Brook University: Scott A. Smolka, Scott Stoller, Erez Zadok, Dung Phan NASA JPL: Klaus Havelund

Partners: Stony Brook University, NASA JPL

Time Frame: started 01. 08. 2014

Contact Persons: Radu Grosu

Research Team: Radu Grosu

The goal of the ARRiVE project is to develop online verification techniques for the monitoring, analysis and guidance of the run-time program execution. Inspired by the Simplex architecture, the aim is to provide a novel extension of runtime verification for cyber-physical systems (CPS) in which runtime verification is itself adaptive. In particular, we plan to investigate overhead control, monitoring in presence of incomplete information, predictive analysis, and a comprehensive Simplex architecture for CPS. We will evaluate the framework performance and utility through significant case studies, including the runtime monitoring of the command-and-control and energy-measurement infrastructure of a fleet of UAVs and a fleet of rovers. The results of our research are going to contribute to the development of complex, adaptive software which have improved reliability and improved robustness.

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New Formal Verification Methods and Concepts for Analog and Mixed Signal Smart Power Systems

Funding: AT-FFG-Basisprogramm within project EM²APS

Partners: AT-KAI, AT-Infineon, AT-AIT

Time Frame: started 01. 07. 2015

Contact Persons: Radu Grosu

Research Team: Radu Grosu, Dieter Haerle, Mikko Vaeaenaenen, Luca Petruzzi, Dejan Nickovic, Josef Fugger

Short product life cycles, increasing complexity and high integrated circuits force the semiconductor industry to continuously improve the development and verification process. The verification process ensures whether a design meets the specification requirements and is accomplished in parallel to the development process. The tight timeline associated with current projects does not allow system design and verification to wait for a real prototype. Therefore most of the system verification tasks have to be done with virtual prototyping using simulation tools. The goal of this activity is to develop and investigate new methods and concepts for verification of Mixed-Signal Smart Power ICs for various automotive applications, like lighting, heating, power distribution, motor driving etc. Short time to market requirements, increasing complexity, miniaturization of modern ICs and latest safety standards result in stringent requirements and considerable effort for the pre-silicon verification process.

Self-stabilizing Byzantine Fault-Tolerant Distributed Algorithms for Integrated Circuits

Funding: Austrian Science Fund (FWF)

Collaborators: Christoph Lenzen (MPI Saarbrücken), Danny Dolev (Hebrew University), Thomas Nowak (ENS Paris), Michael Hofbauer (TU Wien, Institute of Electrodynamics, Microwave and Circuit Engineering)

Time Frame: started 01. 11. 2013

Contact Persons: Ulrich Schmid

Research Team: Ulrich Schmid

The ultimate goal of SIC (Self-stabilizing Byzantine Fault-Tolerant Distributed Algorithms for Integrated Circuits) is to develop the foundations of a framework for the rigorous modeling and analysis of Byzantine fault-tolerant self-stabilizing distributed algorithms for VLSI circuits.

Funding: Austrian Science Fund (FWF), project no P26436

Collaborators: Christoph Lenzen (MPI Saarbrücken), Danny Dolev (Hebrew University), Thomas Nowak (ENS Paris), Michael Hofbauer (TU Wien, Institute of Electrodynamics, Microwave and Circuit Engineering)

Time Frame: 01. 11. 2013-31. 10. 2018

Contact Persons: Matthias Függer (Project Head), Ulrich Schmid

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National Research Network RiSE/SHiNE (PP05)

Funding: Austrian Science Fund (FWF)

Partners: Graz University of Technology (coordinator), Vienna University of Technology, Institute of Science and Technology Austria, Johannes Kepler University Linz, University of Salzburg.

Time Frame: started 01. 03. 2015

Contact Persons: Ulrich Schmid

Research Team: Ulrich Schmid, Ezio Bartocci, Martin Zeiner

RiSE/SHiNE pursues the long term vision of a hardware/software system design process supported by automatic formal methods based on model checking, decision procedures, and game theory. Simultaneously, the National Research Network has the strategic goal to establish and strengthen Austria as an international hot spot in this research area. In the first three years of the 4-year funding period (Period I), we have made important steps towards both the scientific and the strategic goal. A key lesson from Period I was that non-functional aspects of system quality and correctness are critical, hard to achieve manually, and highly amenable to rigorous reasoning. We view the second period of RiSE 2015–2019 as an opportunity to position Computer Aided Verification closer to other fields of computer science which address non-functional aspects in a rigorous manner. In Period II, nine Project Part Leaders and six (mostly) junior Task Leaders will build upon the foundations established in the first years. The new Tasks that we propose either derive from a cross cutting “collaboration topic” of Period I or are new topics introduced by the recently hired faculty. All Tasks will be jointly investigated by two PIs. While the Research Clusters of Period I reflected the individual expertise of the PIs, we will now organize our Tasks along intersecting Research Lines. Each Research Line of Period II will address a non-functional aspect such as concurrency, probabilistic behavior, reliability, and quantitative measures (timing and resource consumption). This focus reflects a broader understanding of correctness beyond the Boolean notion of functional correctness that was central in Period I. Thus, our thrust will go beyond verification of functional specifications to computer aided design of programs that fulfill both functional and non-functional properties. We have therefore subtitled the second funding Period Systematic Methods in Systems Engineering, or SHiNE. SHiNE project part PP05: Reconciling Distributed and Real-Time Computing (Schmid, Bartocci). Modern distributed systems, ranging from systems-on-chip (SoC) to electronic commerce networks, must be resilient to failures and maintain specified response time bounds. The Tasks of PP05 is devoted to a continuous-time modeling & analysis framework for such systems:

    • Task US1: Modeling and Analysis of Distributed Systems with Non-Zero-Time Computations (Applications). The abstraction of discrete, instantaneous state transitions inherently “defines away” queueing and scheduling issues and thus does not adequately match real systems. The situation is even worse in case of algorithms implemented in hardware, as abstracting continuous computations by discrete state transitions “defines away” metastability of discrete-valued signals/states and the impossibility to build an arbiter. The problem is further exacerbated by incorporating fault-tolerance, in particular, self-stabilization, which requires solutions that recover from system states without any synchrony. In a collaboration with PP07 (Chatterjee), which has already been established in RiSE, PP02 (Henzinger) and PP08 (Biere), we will develop the foundations and solution methods for a suitable real-time analysis framework.
    • Task EBUS2: Modeling and Analysis of Parametric, Probabilistic and Parameterized Timed Systems (Ezio Bartocci) (Applications). To master the overwhelming complexity of manual correctness proofs of continuous-time distributed systems, computer-aided methods that can deal with symbolic timing parameters (“parametric”) and symbolic system sizes (“parameterized”) are required. Besides the question of how to deal with the overwhelming complexity, answering the question of how to incorporate (probabilistic) faults will be addressed in collaboration with PP12 (Grosu), PP07 (Chatterjee) and PP11 (Kirsch). In order to extend our framework to also cover message-passing distributed systems with parameterized system size, novel abstraction techniques and/or cutoff results will be developed in a collaboration with PP03 (Veith).

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Accelerator-based Experimental Analysis and Simulation Modeling of Single-Event Transients in VLSI Circuits (EASET)

Funding: FWF stand-alone project

Collaborators: Institute of Electrodynamics, Microwave and Circuit Engineering TU Wien (prof. Zimmermann)

Time Frame: started 01. 04. 2014

Due to the steadily decreasing feature sizes of modern VLSI circuits, which are in the nanometer range (< 100 nm) nowadays, single-event effects (SEEs) are increasingly dominating the fault rate of VLSI circuits. SEEs occur when junctions of transistors are hit by ionized particles. Such particles primarily originate in high-energy cosmic radiation, affecting a chip either directly (at high altitudes, i.e., in space and aerospace) or indirectly, via interaction with the atmosphere. The primary concern in modern VLSI circuits are transient SEEs: An ionized particle deposits charge along its track, which in turn can cause a single-event transient (SET) signal pulse (0.1-1 ns range). If a sufficiently strong SET propagates to a storage element, it can be latched, thereby producing a single-event upset (SEU).

Robust circuit design, in particular, for critical applications, hence needs models that accurately describe SETs/SEUs and are easy and efficient to use at early design stages. Such models both allow (a) to assess the radiation tolerance of different architectural designs and hardening techniques and (b) to estimate the final error rate of a circuit. The preferred method to accomplish this is simulation-based fault injection at the (analog) electrical level: Typically, a Spice model of the circuit (derived automatically from the design using technology libraries) is augmented with Spice models that simulate SET generation in critical parts of the circuit. The most commonly approach here is single-ended injection of a double-exponential current into the drain of a transistor.

Obviously, the suitability of this method for validating the effectiveness of radiation-hardening measures and predicting soft-error rates stands or falls with the availability of accurate Spice models for SET generation: If it fails to cover important scenarios, one might e.g. overlook situations where radiation-hardening fails. Unfortunately, there is evidence that standard double-exponential Spice models are susceptible to such problems, with respect to several aspects: (1) Inadequate model structure, (2) calibration of model parameters, and (3) SEEs affecting multiple transistors.

Any attempt to developing Spice models that accurately model SET generation (including the above complications) in nanometer VLSI circuits requires a combination of both (a) a detailed understanding of the physical/electrical processes involved and (b) a comprehensive experimental evaluation of SET pulses arising in real circuits. The project EASET is devoted to this purpose: It will use results from accurate analog SET measurements in carefully designed measurement ASICs under micro-beam irradiation to (i) guide the development and (ii) calibrate detailed 3D physical/hybrid TCAD simulation models. The latter is a very powerful means for researching the SET generation process and its parameters in VLSI circuits, and thus also the appropriate basis for developing and validating novel SET generation Spice models for complex nanometer VLSI circuits, which are the primary intended outcome of the project.

The measurement ASICs will include on the one hand the circuits under test, e.g. circuits based on basic combinational and sequential logic and possibly some other topologies like ring oscillators. On the other hand the ASICs will include high speed analog measurement amplifiers which must have minimum influence on the investigated circuit nodes, and they have to include high speed analog 50Ω-output drivers. Additional analog high speed multiplexers are necessary due to the large number of investigated circuit nodes. Consequently, EASET not only addresses interesting fundamental research questions, but also provides results that are relevant in practice. The required competence is ensured by running it as a joint project between the Institut für Technische Informatik and the Institute of Electrodynamics, Microwave and Circuit Engineering at TU Wien, which also includes external collaborations with radiation physics experts e.g. at the GSI in Darmstadt and the PTB in Braunschweig.

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