Rachmad Vidya Wicaksana Putra

Rachmad Vidya Wicaksana Putra



Phone +43 (1) 58801-18203
Fax +43 (1) 58801-18297

Vienna University of Technology
Department of Computer Engineering
Embedded Computing Systems
Treitlstraße 3 1040 Wien Österreich

Short Biography

Mr. Rachmad received B.Sc. on Electrical Engineering in 2012 and M.Sc. on Electronics Engineering in 2015, both from Bandung Institute of Technology (ITB), Indonesia. He was an internee at CV. Versatile Silicon Technologies for 2 months and working at PT. Fusi Global Teknologi for almost 2 years. He was also with Bandung Institute of Technology (ITB) as a teaching assistant at Electrical Engineering Department, School of Electrical Engineering and Informatics in 2012-2017 and as a research assistant at Microelectronics Center in 2014-2017. Currently, he is a research assistant and Ph.D. student at Computer Architecture and Robust Energy-Efficient Technologies (CARE-Tech.), Embedded Computing Systems, Institute of Computer Engineering, Technische Universität Wien, under supervision of Prof. Dr. Muhammad Shafique. His research interests mainly include computer architecture, VLSI design, system-on-chip, brain-inspired computing, emerging computing paradigms and technologies.

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Publications with TU Wien

  Conference/Symposium Papers

  1. M. A. Hanif, F. Khalid, R. V. W. Putra, S. Rehman, M. Shafique, “Robust Machine Learning Systems: Reliability and Security for Deep Neural Networks”, IEEE/ACM 24th Symposium on On-Line Testing and Robust System Design (IOLTS), July 2018. (DOI: 10.1109/IOLTS.2018.8474192 | IEEExplore)

  Workshop Papers

  1. A. Marchisio, R. V. W. Putra, M. A. Hanif, M. Shafique, “HW/SW Co-Design and Co-Optimizations for Deep Learning”, Workshop on INTelligent Embedded Systems Architectures and Applications (INTESA), at the Embedded Systems Week (ESWeek), Italy, 04 October 2018. (DOI: 10.1145/3285017.3285022 | ACM Digital Library)


  1. M. A. Hanif, R. V. W. Putra, M. Tanvir, R. Hafiz, S. Rehman, M. Shafique, “MPNA: A Massively-Parallel Neural Array Accelerator with Dataflow Optimization for Convolutional Neural Networks”, arXiv Preprint, arXiv:1810.12910, 30 October 2018. (arXiv:1810.12910