Rachmad Vidya Wicaksana Putra

Rachmad Vidya Wicaksana Putra
Research Staff Projektass.
rachmad_ecs.jpg
E-Mail
Phone +43 (1) 58801-18203
Fax +43 (1) 58801-18297
Address



Vienna University of Technology
Institute of Computer Engineering
Embedded Computing Systems
Treitlstraße 3 1040 Wien Österreich

Short Biography

Mr. Rachmad received B.Sc. on Electrical Engineering in 2012 and M.Sc. on Electronics Engineering in 2015, both from Bandung Institute of Technology (ITB), Indonesia. He was an internee at CV. Versatile Silicon Technologies for 2 months and working at PT. Fusi Global Teknologi for almost 2 years. He was also with ITB as a teaching assistant at Electrical Engineering Department, School of Electrical Engineering and Informatics ITB in 2012-2017 and as a research assistant at Microelectronics Center ITB in 2014-2017. Currently, he is a research assistant and Ph.D. student at Computer Architecture and Robust Energy-Efficient Technologies (CARE-Tech.), Embedded Computing Systems, Institute of Computer Engineering, Technische Universität Wien, under supervision of Prof. Dr. Muhammad Shafique. His research interests mainly include computer architecture & systems, integrated circuits & VLSI design, brain-inspired & neuromorphic computing, robust & energy-efficient computing, and electronic design automation.

Publications with TU Wien

  Book Chapters

  1. M. A. Hanif, F. Khalid, R. V. W. Putra, M. T. Teimoori, F. Kriebel, J. Zhang, K. Liu, S. Rehman, T. Theocharides, A. Artusi, S. Garg, M. Shafique, “Robust Computing for Machine Learning-Based Systems”, in “Dependable Embedded Computing” Book, Springer Science+Business Media, LLC, 2019. (DOI: 10.1007/978-3-030-52017-5_20) [Published: 10.December.2020]

  Journals / Transactions Publications

  1. R. V. W. Putra, M. A. Hanif, M. Shafique, "ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators", IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI). (DOI: 10.1109/TVLSI.2021.3060509 | IEEEXplore) [Accepted 27.January.2021] 
  2. P. Achararit, M. A. Hanif, R. V. W. Putra, M. Shafique, Y. Hara-Azumi, "APNAS: Accuracy-and-Performance-Aware Neural Architecture Search Considering Neural Hardware Accelerators", IEEE Access. (DOI: 10.1109/ACCESS.2020.3022327 | IEEEXplore)  [Accepted 18.August.2020] 
  3. R. V. W. Putra, M. Shafique, "FSpiNN: An Optimization Framework for Memory- and Energy-Efficient Spiking Neural Networks", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Embedded Systems Week (ESWEEK) Special Issue; presented in the International Conferences on Compilers, Architectures, Synthesis for Embedded Systems (CASES), September 2020. (DOI: 10.1109/TCAD.2020.3013049 | IEEEXplore) [Accepted 06.July.2020] 

  Conference / Symposium Publications

  1. R. V. W. Putra, M. Shafique, “Q-SpiNN: A Framework for Quantizing Spiking Neural Networks”, International Joint Conference on Neural Networks (IJCNN), 18-22 July 2021, Shenzhen, China. [Accepted 10.April.2021]
  2. R. V. W. Putra, M. A. Hanif, M. Shafique, “SparkXD: A Framework for Resilient and Energy-Efficient Spiking Neural Network Inference using Approximate DRAM”, IEEE/ACM 58th Design Automation Conference (DAC), December 2021, San Fransisco, CA, USA. [Accepted 24.February.2021 | Acceptance Rate: 23%]
  3. R. V. W. Putra, M. Shafique, “SpikeDyn: A Framework for Energy-Efficient Spiking Neural Networks with Continual and Unsupervised Learning Capabilities in Dynamic Environments”, IEEE/ACM 58th Design Automation Conference (DAC), December 2021, San Fransisco, CA, USA. [Accepted 24.February.2021 | Acceptance Rate: 23%]
  4. R. V. W. Putra, M. A. Hanif, M. Shafique, “DRMap: A Generic DRAM Data Mapping Policy for Energy-Efficient Processing of Convolutional Neural Networks”, IEEE/ACM 57th Design Automation Conference (DAC), July 2020, San Fransisco, CA, USA. (DOI: 10.1109/DAC18072.2020.9218672 | IEEExplore) [Accepted 28.February.2020 | Acceptance Rate: 23%] | Featured in Comet.ml (link) | HiPEAC Paper Award (link)
  5. M. A. Hanif, F. Khalid, R. V. W. Putra, S. Rehman, M. Shafique, “Robust Machine Learning Systems: Reliability and Security for Deep Neural Networks”, IEEE/ACM 24th Symposium on On-Line Testing and Robust System Design (IOLTS), July.2018. (DOI: 10.1109/IOLTS.2018.8474192 | IEEExplore)

  Workshop Papers

  1. A. Marchisio, R. V. W. Putra, M. A. Hanif, M. Shafique, “HW/SW Co-Design and Co-Optimizations for Deep Learning”, Workshop on INTelligent Embedded Systems Architectures and Applications (INTESA), at the Embedded Systems Week (ESWEEK), Italy, 04.October.2018. (DOI: 10.1145/3285017.3285022 | ACM Digital Library)

  CS ArXiv Papers

  1. R. V. W. Putra, M. A. Hanif, M. Shafique, “SparkXD: A Framework for Resilient and Energy-Efficient Spiking Neural Network Inference using Approximate DRAM”, arXiv Preprint, arXiv CS: 2103.00421 (link), 02.March.2021 [Accepted in DAC'21]
  2. R. V. W. Putra, M. Shafique, “SpikeDyn: A Framework for Energy-Efficient Spiking Neural Networks with Continual and Unsupervised Learning Capabilities in Dynamic Environments”,  arXiv Preprint, arXiv CS: 2103.00424 (link), 02.March.2021. [Accepted in DAC'21]
  3. R. V. W. Putra, M. Shafique, "FSpiNN: An Optimization Framework for Memory- and Energy-Efficient Spiking Neural Networks", arXiv Preprint, arXiv CS: 2007.08860 (link), 17.July.2020. [Published in IEEE-TCAD'20]
  4. R. V. W. Putra, M. A. Hanif, M. Shafique, “DRMap: A Generic DRAM Data Mapping Policy for Energy-Efficient Processing of Convolutional Neural Networks”, arXiv Preprint, arXiv CS: 2004.10341 (link), 21.April.2020. Featured in Comet.ml (link)
  5. R. V. W. Putra, M. A. Hanif, M. Shafique, “ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators”, arXiv Preprint, arXiv CS: 1902.10222 (link), 4.February.2019. [Published in IEEE-TVLSI'21]
  6. M. A. Hanif*, R. V. W. Putra*, M. Tanvir, R. Hafiz, S. Rehman, M. Shafique, “MPNA: A Massively-Parallel Neural Array Accelerator with Dataflow Optimization for Convolutional Neural Networks”, arXiv Preprint, arXiv CS:1810.12910 (link), 30.October.2018. (* The authors contributed equally)

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