Faiq Khalid
Projektass. |
![]() |
|
E-Mail: | faiq.khalid@tuwien.ac.at | |
Phone: | +43 (1) 58801-18268 | |
Fax: | +43 (1) 58801-18297 | |
Address: |
Vienna University of Technology Department of Computer Engineering Embedded Computing Systems Group Treitlstrasse 3, 2nd floor, 1040 Wien, Austria |
Research Projects:
Hardware Security
- Run-time Hardware Trojan Monitors through modeling Burst Mode Communication
- A Self-learning Framework to Detect the Intruded Integrated Circuits
- Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification
- Hardware Trojan detection in SE Tolerant Macro Synchronous Micro Asynchronous (MSMA) pipeline
Model Checking
- Formal Verification of Gate-Level Multiple Side Channel Parameters to detect Hardware Trojans
- Formal Analysis of Macro Synchronous Micro Asychronous Pipeline for Hardware Trojan Detection
- CAnDy-TM: Comparative Analysis of Central & Distributed DTM in Many-Cores using Model Checking
- FAMe-TM: Formal Analysis Methodology for Task Migration Algorithms in Many-Core Systems
- Formal Verification of DTM for Thermal Management in On-chip Multi-core Systems using nuXmv
Digital VLSI Design
- Low Power Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline
- Modified Null Convention Logic Pipeline to Detect Soft Errors in Both Null and Data Phase
- Design of A Digital Phase Detector for Clock Synchronization in MPSoC
- Towards Precise, Scalable and Automatic Analysis of Analog and