Faiq Khalid

Projektass.
E-Mail:	faiq.khalid@tuwien.ac.at
Phone:	+43 (1) 58801-18268
Fax:	+43 (1) 58801-18297
Address:	Vienna University of Technology Department of Computer Engineering Embedded Computing Systems Group Treitlstrasse 3, 2nd floor, 1040 Wien, Austria

Research Projects:

Hardware Security

1. Run-time Hardware Trojan Monitors through modeling Burst Mode Communication
2. A Self-learning Framework to Detect the Intruded Integrated Circuits
3. Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification
4. Hardware Trojan detection in SE Tolerant Macro Synchronous Micro Asynchronous (MSMA) pipeline

Model Checking

1. Formal Verification of Gate-Level Multiple Side Channel Parameters to detect Hardware Trojans
2. Formal Analysis of Macro Synchronous Micro Asychronous Pipeline for Hardware Trojan Detection
3. CAnDy-TM: Comparative Analysis of Central & Distributed DTM in Many-Cores using Model Checking
4. FAMe-TM: Formal Analysis Methodology for Task Migration Algorithms in Many-Core Systems
5. Formal Verification of DTM for Thermal Management in On-chip Multi-core Systems using nuXmv

Digital VLSI Design

1. Low Power Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline
2. Modified Null Convention Logic Pipeline to Detect Soft Errors in Both Null and Data Phase
3. Design of A Digital Phase Detector for Clock Synchronization in MPSoC
4. Towards Precise, Scalable and Automatic Analysis of Analog and