Publications

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Journal Papers

J. Maier, H. Detz: Atomistic modeling of interfaces in III-V semiconductor superlattices
Physica Status Solidi B - Basic Solid State Physics, 253 (2016), p. 613 - 622
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Conference Papers

C. Fan, Y. Meng, J. Maier, E. Bartocci, S. Mitra, U. Schmid: Verifying nonlinear analog and mixed-signal circuits with inputs
Proc. of ADHS 2018: the 6th IFAC Conference on Analysis and Design of Hybrid Systems, Oxford, UK; in: Proc. of ADHS 2018: the 6th IFAC Conference on Analysis and Design of Hybrid Systems, IFAC-PapersOnLine, 51 / 16 (2018), p. 241 - 246
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M Függer, J. Maier, R. Najvirt, T. Nowak, U. Schmid: A Faithful Binary Circuit Model with Adversarial Noise
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE'18), Dresden, Deutschland; in: Proceedings of the 2018 Design, Automation & Test in Europe (DATE), 2018, ISBN: 978-3-9819263-1-6, p. 1327 - 1332
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A. Steininger, R. Najvirt, J. Maier: Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior?
2016 Euromicro Conference on Digital System Design (DSD), Limassol, Portugal; in: 2016 Euromicro Conference on Digital System Design (DSD), IEEE, 2016, ISBN: 978-1-5090-2817-7, p. 372 - 379
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A. Steininger, J. Maier, R. Najvirt: The Metastable Behavior of a Schmitt-Trigger
22nd IEEE International Symposium on Asynchronous Circuits and Systems, Porto Alegre -- Brazil; in: 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), IEEE Computer Society Conference Publishing Services (CPS), 2016, ISBN: 978-1-4673-9007-1, p. 57 - 64
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H. Detz, J. Maier, G. Strasser: Atomistic Modeling of Interfacial Strain in III-V Heterostructures
Compound Semiconductor Week (CSW), Santa Barbara; in: 2015 Compound Semiconductor Week, 2015, p. 1 - 2
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J. Maier, H. Detz, G. Strasser: Atomistic Modeling of III-V Semiconductor Interfaces
Vienna Young Scientists Symposium - VSS 2015, Vienna University of Technology; in: VSS - VIENNA young SCIENTISTS SYMPOSIUM, June 25-26 2015, Book-of-Abstracts.com, Heinz A. Krebs, Gumpoldskirchen, Austria (2015), ISBN: 978-3-9504017-0-7, p. 38 - 39
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J. Maier, A. Steininger: Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic
17th Symposium on Design and Diagnosis of Electronic Circuits and Systems (DDECS 2014), Warschau, Polen; in: Design and Diagnostics of Electronic Circuits Systems (DDECS), 2014 IEEE 17th International Symposium on, 2014; 6 pages
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Theses

J. Maier: Modeling III-V Semiconductor Interfaces at an Atomistic Level using Empirical Potentials (Master's Thesis)
reviewers: G. Strasser, H. Detz; E362, 2016; oral examination: 2016-04-14
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J. Maier: Online Test Vector Insertion - A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic (Master's Thesis)
reviewer: A. Steininger; Technische Informatik, 2014
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Presentations

C. Fan, Y. Meng, J. Maier, E. Bartocci, S. Mitra, U. Schmid: Verifying nonlinear analog and mixed-signal circuits with inputs
Proc. of ADHS 2018: the 6th IFAC Conference on Analysis and Design of Hybrid Systems, Oxford, UK; in: Proc. of ADHS 2018: the 6th IFAC Conference on Analysis and Design of Hybrid Systems, IFAC-PapersOnLine, 51 / 16 (2018), p. 241 - 246
bib details doi

M Függer, J. Maier, R. Najvirt, T. Nowak, U. Schmid: A Faithful Binary Circuit Model with Adversarial Noise
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE'18), Dresden, Deutschland; in: Proceedings of the 2018 Design, Automation & Test in Europe (DATE), 2018, ISBN: 978-3-9819263-1-6, p. 1327 - 1332
bib details

A. Steininger, R. Najvirt, J. Maier: Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior?
2016 Euromicro Conference on Digital System Design (DSD), Limassol, Portugal; in: 2016 Euromicro Conference on Digital System Design (DSD), IEEE, 2016, ISBN: 978-1-5090-2817-7, p. 372 - 379
bib details doi

A. Steininger, J. Maier, R. Najvirt: The Metastable Behavior of a Schmitt-Trigger
22nd IEEE International Symposium on Asynchronous Circuits and Systems, Porto Alegre -- Brazil; in: 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), IEEE Computer Society Conference Publishing Services (CPS), 2016, ISBN: 978-1-4673-9007-1, p. 57 - 64
bib details doi

H. Detz, J. Maier, G. Strasser: Atomistic Modeling of Interfacial Strain in III-V Heterostructures
Compound Semiconductor Week (CSW), Santa Barbara; in: 2015 Compound Semiconductor Week, 2015, p. 1 - 2
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J. Maier, H. Detz, G. Strasser: Atomistic Interface Modeling in III-V Semiconductor Superlattices
Gemeinsame Jahrestagung 2015 der ÖPG, SPS, ÖGA und SSAA in Wien, Wien
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J. Maier, H. Detz, G. Strasser: Atomistic Modeling of III-V Semiconductor Interfaces
Vienna Young Scientists Symposium - VSS 2015, Vienna University of Technology; in: VSS - VIENNA young SCIENTISTS SYMPOSIUM, June 25-26 2015, Book-of-Abstracts.com, Heinz A. Krebs, Gumpoldskirchen, Austria (2015), ISBN: 978-3-9504017-0-7, p. 38 - 39
bib details pdf

J. Maier, A. Steininger: Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic
17th Symposium on Design and Diagnosis of Electronic Circuits and Systems (DDECS 2014), Warschau, Polen; in: Design and Diagnostics of Electronic Circuits Systems (DDECS), 2014 IEEE 17th International Symposium on, 2014; 6 pages
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Reports, Miscellaneous

J. Maier: Modeling the CMOS Inverter using Hybrid Systems
TUW-259633, 2017
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