References

@inproceedings{MS14:DDECS,
  key = {2014},
  author = {Maier, J. and Steininger, A.},
  booktitle = {Design and Diagnostics of Electronic Circuits Systems, 17th International Symposium on},
  title = {Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic},
  year = {2014},
  pages = {33-38},
  keywords = {asynchronous circuits;built-in self test;fault tolerance;integrated circuit testing;4-phase data stream;NULL phase;asynchronous logic;concurrent built-in self-testing;elastic timing behaviour;fault-tolerant systems;online test vector insertion;Circuit faults;Delays;Pipelines;Protocols;Rails;Testing;Vectors},
  doi = {10.1109/DDECS.2014.6868759},
  month = apr,
  url = {https://ieeexplore.ieee.org/document/6868759/}
}

@mastersthesis{M14:MSC,
  author = {Maier, J{\"u}rgen},
  title = {Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST)
  Approach for Asynchronous Logic},
  school = {TU Wien, Vienna, Austria},
  year = 2014,
  month = oct,
  note = {Master Thesis, Institute of Computer Engineering, TU Wien, Vienna, Austria},
  url = {http://catalogplus.tuwien.ac.at/UTW:UTW:UTW_alma2139475450003336},
  pdf = {https://ti.tuwien.ac.at/ecs/people/jmaier/m16_msc.pdf}
}

@inproceedings{DMS15:CSW,
  key = {2015},
  author = {Detz, H. and Maier, J. and Strasser, G.},
  booktitle = {2015 Compound Semiconductor Week},
  title = {Atomistic Modeling of Interfacial Strain in III-V Heterostructures},
  year = {2015},
  pages = {1-2},
  keywords = {III-V semiconductors, atomistic modeling},
  month = {June}
}

@inproceedings{MDS15:VSS,
  key = {2015},
  author = {Maier, J. and Detz, H. and Strasser, G.},
  booktitle = {Vienna Young Scientist Symposium},
  title = {Atomistic Modeling of III-V Semiconductor Interfaces},
  year = {2015},
  pages = {38-39},
  keywords = {III-V semiconductors, atomistic modeling},
  month = {June}
}

@mastersthesis{M16:MSC,
  author = {Maier, J{\"u}rgen},
  title = {Modeling III-V Semiconductor Interfaces at an Atomistic Level using Empirical Potentials},
  school = {TU Wien, Vienna, Austria},
  year = 2016,
  month = {April},
  note = {Master Thesis, Institute of Solid State Electronics, TU Wien, Vienna,
Austria},
  url = {http://catalogplus.tuwien.ac.at/UTW:UTW:UTW_alma2150179390003336},
  pdf = {https://owncloud.tuwien.ac.at/index.php/s/Or6ks5abyKauqSL}
}

@article{MD16:PSSB,
  key = {2016},
  author = {Maier, J{\"u}rgen and Detz, Hermann},
  title = {Atomistic modeling of interfaces in III-V semiconductor superlattices},
  journal = {physica status solidi (b)},
  volume = {253},
  number = {4},
  issn = {1521-3951},
  url = {http://dx.doi.org/10.1002/pssb.201552496},
  doi = {10.1002/pssb.201552496},
  pages = {613--622},
  keywords = {III-V semiconductors, atomistic modeling, interfaces, roughness, superlattices},
  year = {2016}
}

@inproceedings{SMN16:ASYNC,
  key = 2016,
  author = {A. Steininger and J. Maier and R. Najvirt},
  booktitle = {2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)},
  title = {The Metastable Behavior of a Schmitt-Trigger},
  year = 2016,
  pages = {57-64},
  keywords = {SPICE;circuit feedback;logic design;mathematical analysis;trigger
                  circuits;CMOS;Marino;SPICE;Schmitt-trigger
                  circuits;mathematical model;metastability handling;positive
                  feedback circuit;Context;Feedback
                  circuits;Hysteresis;Integrated circuit modeling;Mathematical
                  model;Negative feedback;Threshold
                  voltage;Asynchronous;Glitch;Late
                  Transition;Metastability;Positive Feedback
                  Circuit;Schmitt-Trigger},
  doi = {10.1109/ASYNC.2016.19},
  url = {https://ieeexplore.ieee.org/document/7584893/},
  pdf = {https://ti.tuwien.ac.at/ecs/people/jmaier/SMN16_ASYNC.pdf},
  month = {May}
}

@inproceedings{SNM16:DSD,
  key = {2016},
  author = {A. Steininger and R. Najvirt and J. Maier},
  booktitle = {2016 Euromicro Conference on Digital System Design (DSD)},
  title = {Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior?},
  year = {2016},
  pages = {372-379},
  keywords = {Clocks;Hysteresis;Latches;Mathematical
                  model;Robustness;Synchronization;Threshold
                  voltage;Hysteresis;Metastability;Schmitt-Trigger cascade},
  doi = {10.1109/DSD.2016.56},
  url = {https://ieeexplore.ieee.org/document/7723576/},
  month = {aug},
  pdf = {https://ti.tuwien.ac.at/ecs/people/jmaier/SNM16_DSD.pdf}
}

@techreport{M17:TR,
  key = {2017},
  author = {Maier, J{\"u}rgen},
  title = {Modeling the CMOS Inverter using Hybrid Systems},
  institution = {E182 - Institut f{\"u}r Technische Informatik; Technische Universit{\"a}t Wien},
  year = {2017},
  number = {TUW-259633},
  url = {http://publik.tuwien.ac.at/files/publik_259633.pdf}
}

@inproceedings{FMNNS18:DATE,
  author = {M. F{\"u}gger and J. Maier and R. Najvirt and T. Nowak and U. Schmid},
  booktitle = {2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
  title = {A faithful binary circuit model with adversarial noise},
  year = {2018},
  volume = {},
  number = {},
  pages = {1327-1332},
  keywords = {delay circuits;digital circuits;formal verification;network synthesis;IEEE TC 2016;accurate delay models;adversarial noise;delay functions;delay shifts;deterministic delay function;digital circuits;dynamic timing analysis;even adversarial;faithful binary circuit model;faithful digital circuit models;formal verification;generalized involution model;involution delays;mathematical involutions;nondeterministic delay variations;pure inertial delays;random adversarial;static timing analysis;Analytical models;Delays;Digital circuits;Integrated circuit modeling;Logic gates;Tools},
  doi = {10.23919/DATE.2018.8342219},
  issn = {},
  month = {March},
  note = {Nominee for Best Paper Award},
  url = {https://ieeexplore.ieee.org/document/8342219/},
  pdf = {https://ti.tuwien.ac.at/ecs/people/jmaier/FMNNS18_DATE.pdf}
}

@article{FMMBMS18:ADHS,
  title = {Verifying nonlinear analog and mixed-signal circuits with inputs},
  journal = {IFAC-PapersOnLine},
  volume = {51},
  number = {16},
  pages = {241 - 246},
  year = {2018},
  note = {6th IFAC Conference on Analysis and Design of Hybrid Systems ADHS 2018},
  issn = {2405-8963},
  doi = {10.1016/j.ifacol.2018.08.041},
  url = {http://www.sciencedirect.com/science/article/pii/S2405896318311571},
  pdf = {https://ti.tuwien.ac.at/ecs/people/jmaier/FMMBMS18_ADHS.pdf},
  author = {Chuchu Fan and Yu Meng and J{\"u}rgen Maier and Ezio Bartocci and Sayan Mitra and Ulrich Schmid},
  abstract = {We present a new technique for verifying nonlinear and hybrid models with inputs. We observe that once an input signal is fixed, the sensitivity analysis of the model can be computed much more precisely. Based on this result, we propose a new simulation-driven verification algorithm and apply it to a suite of nonlinear and hybrid models of CMOS digital circuits under different input signals. The models are low-dimensional but with highly nonlinear ODEs, with nearly hundreds of logarithmic and exponential terms. Some of our experiments analyze the metastability of bistable circuits with very sensitive ODEs and rigorously establish the connection between metastability recovery time and sensitivity.}
}

@inproceedings{MFNS19:ASYNC,
  title = {{Transistor-Level Analysis of Dynamic Delay Models}},
  author = {J. Maier and M. F{\"u}gger and T. Nowak and U. Schmid},
  year = {2019},
  note = {accepted for ASYNC'19},
  volume = {},
  number = {},
  pages = {},
  keywords = {Circuit models, glitch propagation, delay models, pulse degradation, model parameterization},
  doi = {},
  issn = {},
  month = {}
}

@inproceedings{MS19:ASYNC,
  title = {{Efficient Metastability Characterization for Schmitt-Triggers}},
  author = {J. Maier and A. Steininger},
  year = {2019},
  note = {accepted for ASYNC'19},
  volume = {},
  number = {},
  pages = {},
  keywords = {},
  doi = {},
  issn = {},
  month = {}
}

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