Jürgen Maier

Dipl.-Ing. Dipl.-Ing. BSc profilePic  
Phone +43 (1) 58801 18259
Fax +43 (1) 58801-18297

TU Wien
Department of Computer Engineering
Embedded Computing Systems
Treitlstrasse 3, 2nd floor, 1040 Wien, Austria

About myself

I am currently working on my PhD thesis as a university assistant at the Embedded Computing Systems Group at the institute of computer engineering at the TU Wien. Before that I received a master degree in “computer engineering” (2014) and a master degree in “microelectronics and photonics” (2016) from TU Wien. A full curriculum vitae is available here.


My main research interest is simple and accurate modeling of clockless asynchronous circuits and its underlying devices ranging from a very high systematic level down to the transistor level. This includes:

  • design of (Q)DI circuits
  • digital delay predictions
  • analytic model characterization
  • metastability analysis
  • transistor level implementations


In the following selected publications are shown. A full list can be found here.

[1] M. Függer, J. Maier, R. Najvirt, T. Nowak, and U. Schmid. A faithful binary circuit model with adversarial noise. In 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pages 1327--1332, March 2018. [ bib | DOI | http ]
[2] C. Fan, Y. Meng, J. Maier, E. Bartocci, S. Mitra, and U. Schmid. Verifying nonlinear analog and mixed-signal circuits with inputs. In tba, page tba, 2018. accepted for ADHS'18. [ bib ]
[3] Jürgen Maier. Modeling the cmos inverter using hybrid systems. Technical Report TUW-259633, E182 - Institut für Technische Informatik; Technische Universität Wien, 2017. [ bib | .pdf ]
[4] A. Steininger, R. Najvirt, and J. Maier. Does cascading schmitt-trigger stages improve the metastable behavior? In 2016 Euromicro Conference on Digital System Design (DSD), pages 372--379, aug 2016. [ bib | DOI | http ]
[5] A. Steininger, J. Maier, and R. Najvirt. The metastable behavior of a schmitt-trigger. In 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pages 57--64, May 2016. [ bib | DOI | http ]
[6] Jürgen Maier. Modeling iii-v semiconductor interfaces at an atomistic level using empirical potentials. Master's thesis, TU Wien, Vienna, Austria, April 2016. Master Thesis, Institute of Solid State Electronics, TU Wien, Vienna, Austria. [ bib | http | http ]
[7] Jürgen Maier and Hermann Detz. Atomistic modeling of interfaces in iii-v semiconductor superlattices. physica status solidi (b), 253(4):613--622, 2016. [ bib | DOI | http ]
[8] H. Detz, J. Maier, and G. Strasser. Atomistic modeling of interfacial strain in iii-v heterostructures. In 2015 Compound Semiconductor Week, pages 1--2, June 2015. [ bib ]
[9] J. Maier, H. Detz, and G. Strasser. Atomistic modeling of iii-v semiconductor interfaces. In Vienna Young Scientist Symposium, pages 38--39, June 2015. [ bib ]
[10] Jürgen Maier. Online test vector insertion: A concurrent built-in self-testing (cbist) approach for asynchronous logic. Master's thesis, TU Wien, Vienna, Austria, October 2014. Master Thesis, Institute of Computer Engineering, TU Wien, Vienna, Austria. [ bib | http | .pdf ]
[11] J. Maier and A. Steininger. Online test vector insertion: A concurrent built-in self-testing (cbist) approach for asynchronous logic. In Design and Diagnostics of Electronic Circuits Systems, 17th International Symposium on, pages 33--38, April 2014. [ bib | DOI | http ]


Created: 2018-10-25 Thu 14:13

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