Jürgen Maier

Jürgen Maier
Univ.Ass. Dipl.-Ing. Dipl.-Ing. BSc
ORCID iD iconhttps://orcid.org/0000-0002-0965-5746

profilePic
E-Mail
Phone +43 (1) 58801 18259
Address



TU Wien
Institute of Computer Engineering
Embedded Computing Systems
Treitlstrasse 3, 2nd floor, 1040 Wien, Austria

Research

My main research interest is explaining and predicting the behavior of digital circuits on a very high level based on analysis made at a lower level, i.e., transistor level. Especially of interest are for me clockless, asynchronous circuits which is for me a very thrilling way to design circuits. These points include:

  • design (flow) of (Q)DI circuits
  • digital delay predictions
  • analytic model characterization
  • metastability analysis
  • transistor level implementations and optimizations

Other responsibilities

  • Member of the Scientific Staff Council (SSC)
  • Member of the Studienkommission for the new master course “Computation Science and Engineering”

About myself

I am currently working on my PhD thesis as a university assistant at the Embedded Computing Systems Group at the institute of computer engineering at TU Wien. Before that I received a master degree in “computer engineering” (2014) and a master degree in “microelectronics and photonics” (2016) from TU Wien. A full curriculum vitae is available here.

Most of my spare time I spend on my duties as a voluntary fire fighter and on constructing various things out of wood to repair/improve our home.

Publications

In the following selected publications are shown. A full list can be found here.

[1] D. Öhlinger, J. Maier, M. Függer, and U. Schmid. The Involution Tool for Accurate Digital Timingand Power Analysis. In 2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 1--8, July 2019.
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[2] P. Paulweber, J. Maier, and J. Cortadella. Unified (A)Synchronous Circuit Development. In 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2019. Fresh idea accepted for ASYNC'19.
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[3] J. Maier and A. Steininger. Efficient Metastability Characterization for Schmitt-Triggers. In 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pages 124--133, May 2019.
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[4] J. Maier, M. Függer, T. Nowak, and U. Schmid. Transistor-Level Analysis of Dynamic Delay Models. In 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pages 76--85, May 2019.
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[5] M. Függer, J. Maier, R. Najvirt, T. Nowak, and U. Schmid. A faithful binary circuit model with adversarial noise. In 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pages 1327--1332, March 2018. Nominee for Best Paper Award.
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[6] Chuchu Fan, Yu Meng, Jürgen Maier, Ezio Bartocci, Sayan Mitra, and Ulrich Schmid. Verifying nonlinear analog and mixed-signal circuits with inputs. IFAC-PapersOnLine, 51(16):241 -- 246, 2018. 6th IFAC Conference on Analysis and Design of Hybrid Systems ADHS 2018.
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[7] Jürgen Maier. Modeling the CMOS Inverter using Hybrid Systems. Technical Report TUW-259633, E182 - Institut für Technische Informatik; Technische Universität Wien, 2017.
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[8] A. Steininger, R. Najvirt, and J. Maier. Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? In 2016 Euromicro Conference on Digital System Design (DSD), pages 372--379, aug 2016.
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[9] A. Steininger, J. Maier, and R. Najvirt. The Metastable Behavior of a Schmitt-Trigger. In 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pages 57--64, May 2016.
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[10] Jürgen Maier. Modeling III-V Semiconductor Interfaces at an Atomistic Level using Empirical Potentials. Master's thesis, TU Wien, Vienna, Austria, April 2016. Master Thesis, Institute of Solid State Electronics, TU Wien, Vienna, Austria.
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[11] Jürgen Maier and Hermann Detz. Atomistic modeling of interfaces in III-V semiconductor superlattices. physica status solidi (b), 253(4):613--622, 2016.
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[12] H. Detz, J. Maier, and G. Strasser. Atomistic Modeling of Interfacial Strain in III-V Heterostructures. In 2015 Compound Semiconductor Week, pages 1--2, June 2015.
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[13] J. Maier, H. Detz, and G. Strasser. Atomistic Modeling of III-V Semiconductor Interfaces. In Vienna Young Scientist Symposium, pages 38--39, June 2015.
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[14] Jürgen Maier. Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic. Master's thesis, TU Wien, Vienna, Austria, October 2014. Master Thesis, Institute of Computer Engineering, TU Wien, Vienna, Austria.
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[15] J. Maier and A. Steininger. Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic. In Design and Diagnostics of Electronic Circuits Systems, 17th International Symposium on, pages 33--38, April 2014.
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Created: 2019-11-19 Tue 14:23

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