Daniel Müller-Gritschneder
Univ.Prof. Dr.-Ing. Dipl.-Ing.
Research Focus
- Computer Engineering: 100%
Research Areas
- Computer Engineering, Embedded Systems, Embedded System Design, Computer Architecture, RISC-V, computer security, Edge AI
About
I am full professor of Computer Architecture at the Institute of Computer Engineering, TU Wien Informatics, Austria, since 2024. Previously, I was a research group leader at the Chair of Electronic Design Automation and acting professor for Real-time Systems at TU Munich, Germany. I received my Dipl.-Ing., Dr.-Ing. and Habilitation degree from TUM in 2003, 2009 and 2019 respectively.
I like working in collaborative research projects in close cooperation with industry partners and in the past cooperated with companies such as Infineon, Bosch, SPARX Systems, BMW and Mercedes.
I often serve in committees for EDA conferences such as DAC, ICCAD, DATE, SAMOS and CODES/ISSS. I am also active in the RISC-V community and co-initiator and steering committee member of the RISC-V Summit Europe. I am senior member of IEEE.
My main research interests are in Electronic System Level Design, RISC-V domain-specific architectures, tinyML/embedded ML compiler toolchains as well as functional safety and HW security.
Roles
- Full Professor
Embedded Computing Systems, E191-02 - Head of Research Unit
Embedded Computing Systems, E191-02 - Curriculum Commission for Computer Engineering
Chair
Contact
- daniel.mueller-gritschneder@tuwien.ac.at
- 1040 Wien, Treitlstrasse 3 / Room DE0218
- vCard from TISS
- ti.tuwien.ac.at/ecs/people/daniel-mueller-gritschneder
- orcid.org/0000-0003-0903-631X
- informatics.tuwien.ac.at/people/daniel-mueller-gritschneder
- tiss.tuwien.ac.at/person/396715
Courses
Summer 2026
- Bachelor Thesis for Computer Science and Business Informatics / 182.698 PR
- Computer Engineering Practical / 191.005 PR
- Computer Engineering Project / 191.006 PR
- Computer Systems / 191.003 VU
- Digital Design and Computer Architecture / 191.016 LU
- Doctorand's seminar / 182.070 SE
- Project in Computer Science 1 / 191.008 PR
- Project in Computer Science 2 / 191.009 PR
- Scientific Project Computer Engineering / 191.007 PR
- Seminar Computer Engineering / 182.757 SE
- Seminar for Master Students in Software Engineering (Computer Engineering) / 180.011 SE
- Special Topics on Memory-Centric Computing / 199.033 VU
- System-Level Design of Embedded Systems / 199.036 VU
Winter 2025
- Advanced Computer Architecture / 191.019 VU
- Bachelor Thesis for Computer Science and Business Informatics / 182.698 PR
- Computer Engineering Practical / 191.005 PR
- Computer Engineering Project / 191.006 PR
- Doctorand's seminar / 182.070 SE
- Project in Computer Science 1 / 191.008 PR
- Project in Computer Science 2 / 191.009 PR
- Scientific Project Computer Engineering / 191.007 PR
- Scientific Research and Writing / 193.052 SE
- Seminar Computer Engineering / 182.757 SE
Projects
- 2025 – 2028 / Austrian Research Promotion Agency (FFG)
- 2025 – 2026 / XCoorp GmbH
- 2025 – 2026 / TÜV Austria Holding AG
Publications
- van Kempen, P., Hager-Clukas, A., Müller-Gritschneder, D., Schlichtmann, U. (2025). GenIE: Reuse-Oriented Generation of Domain-Specific Instruction Extensions. In 2025 IEEE Nordic Circuits and Systems Conference (NorCAS). IEEE Nordic Circuits and Systems Conference (NorCAS 2025), Riga, Latvia. IEEE. Peer-reviewed.
- Klotz, S., Joglekar, N., Bucksch, T., Goswami, D., Müller-Gritschneder, D. (2025). Embedding Current Constraints in Reinforcement Learning for Electric Motor Control. In 2025 IEEE PES 35th Australasian Universities Power Engineering Conference (AUPEC). IEEE PES 35th Australasian Universities Power Engineering Conference (AUPEC 2025), Brisbane, Australia. IEEE. Peer-reviewed.
- Jones, J. P., Van Kempen, P., Mueller-Gritschneder, D. (2025). Vicuna2.0: RISC-V Embedded Vector Unit with Half-Precision Floating-Point Support for TinyML. In 2025 Austrochip Workshop on Microelectronics (Austrochip) (pp. 69–72). IEEE. Peer-reviewed.
- Thoma, M., Aghajanzadeh, E., Balamuthu Sampath, S., Mori, P., Fasfous, N., Frickenstein, A., Vemparala, M.-R., Mueller-Gritschneder, D., Schlichtmann, U. (2025). SuperFast: Fast Supernet Training Using Initial Knowledge. In 2025 62nd ACM/IEEE Design Automation Conference (DAC) (pp. 1–7). IEEE. Peer-reviewed.
- Thoma, M., Villasante, J., Aghajanzadeh, E., Balamuthu Sampath, S., Mori, P., Groetzinger, M., Dylkin, D., Vemparala, M.-R., Fasfous, N., Frickenstein, A., Mueller-Gritschneder, D., Schlichtmann, U. (2025). Flar-SVD: Fast and Latency-Aware Singular Value Decomposition for Model Compression. In 2025 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW) (pp. 1889–1898). IEEE. Peer-reviewed.
- Thoma, M., Tobias Preintner, Aghajanzadeh, E., Balamuthu Sampath, S., Mori, P., Fasfous, N., Vemparala, M.-R., Frickenstein, A., Mueller-Gritschneder, D., Schlichtmann, U. (2025). Uncertainty Aware Training to Improve Uncertainty Active Learning for Semantic Segmentation. In 2025 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW) (pp. 4401–4411). IEEE. Peer-reviewed.
- Klotz, S., Kulkarni, S., Joglekar, N., Bucksch, T., Goswami, D., Mueller-Gritschneder, D. (2025). Sim-to-Real: Tiny Deep Learning Agents on Resource-Constrained Embedded Microcontrollers. In 2025 IEEE Conference on Control Technology and Applications (CCTA) (pp. 806–811). IEEE. Peer-reviewed.
- Ahmadifarsani, S., Müller-Gritschneder, D., Schlichtmann, U. (2025). A High-Level Compiler Integration Approach for Deep Learning Accelerators Supporting Abstraction and Optimization. arXiv.
- Kappes, J., Geier, J., van Kempen, P., Mueller-Gritschneder, D., Schlichtmann, U. (2025). Automated Graph-level Passes for TinyML Fault Tolerance. In 2025 International Joint Conference on Neural Networks (IJCNN). 2025 International Joint Conference on Neural Networks (IJCNN), Rome, Italy. IEEE. Peer-reviewed.
- Rüb, M., Konegen, D., Selle, P., Sikora, A., Müller-Gritschneder, D. (2025). DRIP: DRop unImportant data Points -- Enhancing Machine Learning Efficiency with Grad-CAM-Based Real-Time Data Prioritization for On-Device Training. arXiv.
- Geier, J., Kontopoulos, L., Müller-Gritschneder, D., Schlichtmann, U. (2025). Rapid Fault Injection Simulation by Hash-Based Differential Fault Effect Equivalence Checks. In 2025 Design, Automation Test in Europe Conference (DATE). 2025 Design, Automation Test in Europe Conference (DATE), Lyon, France. IEEE. Peer-reviewed.
- Rüb, M., Konegen, D., Sikora, A., Mueller-Gritschneder, D. (2025). DRIP: DRop unImportant data Points - Enhancing Machine Learning Efficiency with Grad-CAM-Based Streaming Data Prioritization for On-Device Training. In 2025 International Joint Conference on Neural Networks (IJCNN). 2025 International Joint Conference on Neural Networks (IJCNN), Rome, Italy. IEEE. Peer-reviewed.
- Körber, N., Kromer, E., Siebert, A., Hauke, S., Mueller-Gritschneder, D., Schuller, B. (2025). EGIC: Enhanced Low-Bit-Rate Generative Image Compression Guided by Semantic Segmentation. In A. Leonardis, E. Ricci, S. Roth (Eds.), Computer Vision – ECCV 2024 : 18th European Conference, Milan, Italy, September 29 – October 4, 2024, Proceedings, Part XXXV (pp. 202–220). Springer. Peer-reviewed.
- van Kempen, P., Salmen, M., Müller-Gritschneder, D., Schlichtmann, U. (2024). Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization. In Proceedings 2024 27th Euromicro Conference on Digital System Design (DSD 2024) (pp. 335–342). Peer-reviewed.
- Foik, C., Kunzelmann, R., Mueller-Gritschneder, D., Schlichtmann, U. (2024). Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 43(11), 4130–4141. Peer-reviewed.
- Hoffman, A., Fnayou, A., Smirnov, F., Müller-Gritschneder, D., Schlichtmann, U. (2024). MuDSE: GA-ILP-based Framework for Automated Deployment of Multiple DNNs on Heterogeneous Mixed-Criticality Systems. In 2024 IEEE International Conference on Omni-layer Intelligent Systems (COINS). IEEE COINS 2024: IEEE International Conference on Omni-layer Intelligent systems, London, United Kingdom of Great Britain and Northern Ireland (the). IEEE. Peer-reviewed.
Presentations
- Müller-Gritschneder, D., Lieber, P. (2025, August 16). Combining TinyML Model-based Architecture Methods for Predictive Maintenance in Highly Regulated Environments [Presentation]. AI Solution Days 2025, Nürnberg, Germany.HDL: 20.500.12708/219807
- Müller-Gritschneder, D. (2025, June 25). Towards an Automated Toolchain and Fusion-based Instruction Identification for RISC-V Custom Extensions [Conference Presentation]. 2nd Austrian RISC-V Meetup, Graz, Austria.HDL: 20.500.12708/220428
- Müller-Gritschneder, D. (2025, May 30). Low Overhead Fault Tolerance for tinyML and Security Applications [Presentation]. 3rd Workshop on Intelligent Methods for Test and Reliability, Tallinn, Estonia. Invited.HDL: 20.500.12708/219806
- Müller-Gritschneder, D. (2024, September 11). Rapid Prototyping Methods for custom-tailored, safe and secure RISC-V processors [Conference Presentation]. TRISTAN Technical Conference 2024, Graz, Austria.HDL: 20.500.12708/206261
- Mueller-Gritschneder, D., Geier, J. (2024, September). Open Source Simulators for Pre-Silicon Validation of Safety-critical RISC-V System-on-chip [Conference Presentation]. Open Source Summit 2024, Wien, Austria.HDL: 20.500.12708/206489
Theses
- Schloms, D. (2025). Fast simulation and performance estimation for vector co-processors [Diploma Thesis, Technische Universität Wien]. reposiTUm.DOI: 10.34726/hss.2025.131180 / Download: PDF
Awards
- Best Paper Award: Moritz Thoma, Tobias Preintner, Emad Aghajanzadeh, Shambhavi Balamuthu Sampath, Pierpaolo Mori, Nael Fasfous, Manoj-Rohit Vemparala, Alexander Frickenstein, Daniel Mueller-Gritschneder, Ulf Schlichtmann; Uncertainty Aware Training to Improve Uncertainty Active Learning for Semantic Segmentation Proceedings of the Computer Vision and Pattern Recognition Conference (CVPR) Workshops, 2025
2025 / SAIAD Workshop, CVPR25 / USA / Website - Best Student Paper Award: Pierpaolo Mori, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Moritz Thoma, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Christian Unger, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone "Wino Vidi Vici: Conquering Numerical Instability of 8-Bit Winograd Convolution for Accurate Inference Acceleration on Edge"
2024 / IEEE/CVF Winter Conference on Applications of Computer Vision 2024 / USA - Best Paper Award: Samira Ahmadi, Rafael Stahl, Philipp van Kempen, Daniel Mueller-Gritschneder and Ulf Schlichtmann. "Towards Rapid Exploration of Heterogeneous TinyML Systems using Virtual Platforms and TVM’s UMA."
2023 / Workshop on Compilers, Deployment, and Tooling for Edge AI. / Germany - Habilitationspreis
2019 / Bund der Freunde der technischen Universität München / Germany / Website - Best Paper Award for Paper: Saman Payvar, Mir Khan, Rafael Stahl, Daniel Mueller-Gritschneder, Jani Boutellier "Neural Network-based Vehicle Image Classification for IoT Devices"
2019 / IEEE International Workshop on Signal Processing Systems, SiPS 2019 / China - Senior Member
2019 / IEEE / USA
And more…
Soon, this page will include additional information such as reference projects, activities as journal reviewer and editor, memberships in councils and committees, and other research activities.
Until then, please visit Daniel’s research profile in TISS.
Short Bio
Daniel Mueller-Gritschneder is full professor of Computer Architecture at the Institute of Computer Engineering, TU Wien Informatics, Austria, since 2024. Previously, he spend more than 25 years at TU Munich (TUM), from his diploma studies, as a PhD researcher and PostDoc research group leader at the Chair of Electronic Design Automation to acting professor for Real-time Systems. He received his Dipl.-Ing., Dr.-Ing. and Habilitation degree from TUM in 2003, 2009 and 2019 respectively. He has been working in collaborative research projects in close cooperation with industry partners and cooperated with companies such as Infineon, Bosch, SPARX Systems, BMW and Mercedes. He is senior member of IEEE.
Currently the Computer Architecture Group works on:
- Edge AI, Embedded ML, tinyML, especially ML compilers
- Domain-specific RISC-V architectures
- Pre-silicon simulators
- Fault tolerance for safety-critical applications
- HW Security - especially fault attacks
I am or have been involved in the following conferences and workshops in different roles:
- RISC-V Summit Europe
- International Conference on Computer-aided Design (ICCAD)
- International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS)
- ACM/IEEE Design Automation Conference (DAC)
- International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)
- Workshop „Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen” (MBMV)
- Euromicro Conference on Digital System Design (DSD)
- International Conference on VLSI Design & International Conference on Embedded Design (VLSID)
- Workshop on RISC-V Activities
- International Workshop on Embedded Software for Industrial IoT (ESIIT)
- International Workshop on Resiliency in Embedded Electronic Systems (REES)
- HiPEAC International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISEC)
Previous Projects
Before my time at TU Wien, I was involved in the following projects during my time at TU Munich:
- 2025-2028 BMBF Project Open-Source-Designwerkzeuge für die Verifikation von Prozessoren und digitalen Schaltungen (DI-OSVISE)
- 2024-2025 BMBF Project Plattform für energieeffiziente KI-Prozessoren in mobilen Anwendungen (ZuSE KI Mobil)
- 2024-2028 Bavarian Chip Design Center (BCDC) 2023-2026 ITEA4 Project Generating and Deploying Lightweight, Secure and Zero-overhead Software for Multipurpose IoT Devices (GenerIoT)
- 2022-2026 EU Chips JU Project Together for RISc-V Technology and ApplicatioNs (TRISTAN)
- 2022-2025 BMBF Project Flexibles Deployment für HW-agnostische, eingebettete KI Anwendungen (FlexKI)
- 2022-2025 PENTA Project Ecological Motor Control and Predictive Maintenance with AI (ECOMAI)
- 2020-2025 BMBF Project Skalierbare Infrastruktur für Edge-Computing (Scale4Edge)
- 2019-2022 IUK-Programm (Masterplan Bayern Digital II: Bekanntmachung IT-Sicherheit): Maßnahmen der IT-Sicherheit zur hochsicheren Hardware-Industrialisierung (MITHRIL)
- 2019-2021 KME Kompetenzzentrum Mittelstand GmbH – Industrie-Förderprojekt TDD-ViP: Agile testgetriebene Entwicklung eingebetteter Software basierend auf virtuellen Prototypen
- 2018-2022 DFG Transregio/SFB 89 Invasives Rechnen (InvasIC) – PI für Subproject „Generation of Distributed Monitors and Run-Time Verification of Invasive Applications"
- 2017-2020 ITEA3/BMBF Project Cost-Efficient Smart System Software Synthesis (COMPACT);
- 2017-2021 BMBF Project Sicherer Automatischer Software-Entwurf für Industrieanlagen (SAFE4I)
- 2017-2019 BMBF Cluster-Project Automatisierter Firmware-Entwurf für anwendungsspezifische Elektroniksysteme (CONFIRM)
- 2014-2016 DFG Sachbeihilfe SCHL347-3-1: Application of a Generative Grammar for the Automated Architectural Exploration of Digital System-on-Chip (SoC) Platforms
- 2013-2016 BMBF Project Effiziente Fehlereffektsimulation mit virtuellen Prototypen zur Qualifikation intelligenter Motion-Control-Systeme in der Industrieautomatisierung (EffektiV)
- 2011-2017 DFG SPP 1500 Dependable Embedded Systems, Sub-Project “Lifting Device-Level Characteristics for Error Resilient System Level Design: A Crosslayer Approach”