Andreas Steininger

Ao.Univ.Prof. Dipl.-Ing. Dr.techn.

Research Focus

Computer Engineering: 100%

Research Areas

Timing domain interfacing, Clockless Processors, Dependable Computer Systems, Error Detection Mechanisms, Fault Tolerance, Computer Architecture, Built in Self Test (BIST)

About

Asynchronous Logic, Fault Tolerant Clocking, Timing Domain Interfacing (Metastability), Fault Tolerant Architectures, Radiation Effects in Micorelectronics, Fault Injection, trustworthy systems, sustainable computing, computer engineering

Roles

Doctoral School
Director
Associate Professor
Embedded Computing Systems, E191-02
Curriculum Commission for Computer Engineering
Substitute Member

Contact

andreas.steininger@tuwien.ac.at
+43-1-58801-18251
1040 Wien, Treitlstrasse 3 / Room DE0232
vCard from TISS

Courses

Summer 2026

Bachelor Thesis for Computer Science and Business Informatics / 182.698 PR
Computational Bioengineering / 199.035 VU
Computer Engineering Practical / 191.005 PR
Computer Engineering Project / 191.006 PR
Current Trends in Computer Science / 195.072 VU
Digital Design and Computer Architecture / 191.016 LU
Doctorand's seminar / 182.070 SE
Fundamental research methods for doctoral students / 195.079 VU
Industrial Hardware Verification / 191.014 VU
Introduction to Quantum Algorithms / 199.022 VU
Project in Computer Science 1 / 191.008 PR
Project in Computer Science 2 / 191.009 PR
ProWriting -- Effective Research Project Proposal Writing for Public Funding / 195.109 VU
Scientific Project Computer Engineering / 191.007 PR
Seminar Computer Engineering / 182.757 SE
Seminar for Master Students in Computer Engineering / 180.778 SE
Seminar for Master Students in Software Engineering (Computer Engineering) / 180.011 SE
Special Topics on Memory-Centric Computing / 199.033 VU
System-Level Design of Embedded Systems / 199.036 VU

Winter 2025

Advanced Digital Design / 182.755 VU
Advanced Topics in Verification and Synthesis for AI-Enabled Cyber-Physical Systems / 199.030 VU
Bachelor Thesis for Computer Science and Business Informatics / 182.698 PR
Computer Engineering Practical / 191.005 PR
Computer Engineering Project / 191.006 PR
Current Trends in Computer Science / 195.072 VU
Digital Design / 182.693 VO
Doctorand's seminar / 182.070 SE
From surviving to thriving: crafting your good professional life / 199.096 VU
Hardware Modeling / 191.011 VU
HW/SW Codesign / 182.700 VU
Knowledge Representation for Robotics, Automotive, and SmartCities / 199.031 VU
Orientation Bachelor with Honors of Informatics and Business Informatics / 180.767 SE
Philosophy of Science / 195.080 VU
Project in Computer Science 1 / 191.008 PR
Project in Computer Science 2 / 191.009 PR
Propädeutikum für Informatik / 180.771 VU
Scientific Project Computer Engineering / 191.007 PR
Scientific Research and Writing / 193.052 SE
Seminar Computer Engineering / 182.757 SE
Seminar for Master Students in Computer Engineering / 180.778 SE
SMT Solving Internals / 199.029 VU
Weighted Automata and Weighted Logics / 199.032 VU

Projects

TA-CPS: Trustworthy Autonomous Cyber-Physical Systems
2023 – 2028 / TTTech Auto AG / Publications (3)
Intel CARS 2: Robust Atomic Computing Platform and Enhanced Fault-Tolerant Distributed Algorithms 2
2019 – 2028 / Intel Corporation
Intel CARS: Robust Atomic Computing Platform and Enhanced Fault-Tolerant Distributed Algorithms
2017 – 2019 / Intel Corporation / Publications (3)
EASET: Analysis & Modeling of Single-Event-Transients in VLSI Chips
2014 – 2017 / Austrian Science Fund (FWF) / Publications (4)
SIC: Self-stabilizing Byzantine Fault-Tolerant Distributed Algorithms for Integrated Circiuts
2013 – 2018 / Austrian Science Fund (FWF) / Publication
CDPP: Configurable Data Prcessing Platform
2013 – 2014 / Austrian Research Promotion Agency (FFG)
MMU: Fehleranalyse MMU
2012 / Robert Bosch GmbH
CEVTES: CounterExample Validation and Test Case Generation Framework for Verifiying Embedded Software
2010 – 2013 / Austrian Research Promotion Agency (FFG) / Publications (10)
ARTS: Asynchronous Logic in Real-Time Systems
2007 – 2011 / Austrian Research Promotion Agency (FFG) / Publications (6)
DARTS: Distributed Algorithms for Robust Tick Synchronization
2005 – 2010 / Austrian Research Promotion Agency (FFG) / Website / Publications (18)
EXTRACT: Exploiting Synchrony for Transparent Communication Services Testing
2005 – 2008 / Austrian Research Promotion Agency (FFG) / Website / Publications (10)
STEACS: Systematic Test of Embedded Automotive Communication Systems
2003 – 2008 / Austrian Research Promotion Agency (FFG) / Publications (19)

Publications

2025

El Shahaby, R., Függer, M., Huemer, F., Steininger, A. (2025). SeAL: A Provably Complete Fault-Injection Tool for Asynchronous Circuits. In 2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS). 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS 2025), Marrakech, Morocco. IEEE. Peer-reviewed.
DOI: 10.1109/ICECS66544.2025.11270590
Scharwitzl, C., Steininger, A. (2025). Circuits for Autonomous Clock Frequency Supervision. JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 34(18), Article 2543005. Peer-reviewed.
DOI: 10.1142/S0218126625430054
Lehninger, P., Jantsch, A., Steininger, A., Worsey, E., Marot, V., Pamunuwa, D. (2025). Muller C-Element for NEMS. In 2025 29th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) (pp. 56–62). IEEE. Peer-reviewed.
DOI: 10.34726/10060 / Download: PDF
Elshehaby, R., Függer, M., Huemer, F. F., Steininger, A. (2025). Investigating the Effects of Permanent Faults in QDI Circuits: A Formal Perspective. In 2025 29th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) (pp. 142–150). IEEE. Peer-reviewed.
DOI: 10.1109/ASYNC65240.2025.00027

2024

Fiedler, C., Huemer, F., Steininger, A. (2024). Synchronizing Independent Ring Oscillators on an FPGA. In 2024 Austrochip Workshop on Microelectronics (Austrochip) (pp. 1–4). Peer-reviewed.
DOI: 10.1109/Austrochip62761.2024.10716225
Colucci, A., Steininger, A., Shafique, M. (2024). EISFINN: On the Role of Efficient Importance Sampling in Fault Injection Campaigns for Neural Network Robustness Analysis. In 2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS). 2024 IEEE 30th International Symposium on On-line Testing and Robust System Design (IOLTS), Rennes, Brittany, France. IEEE. Peer-reviewed.
DOI: 10.1109/IOLTS60994.2024.10616075
Colucci, A., Steininger, A., Shafique, M. (2024). SBanTEM: A Novel Methodology for Sparse Band Tensors as Soft-Error Mitigation in Sparse Convolutional Neural Networks. In 2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS). 2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS), Rennes, Brittany, France. IEEE. Peer-reviewed.
DOI: 10.1109/IOLTS60994.2024.10616070
Wiedemann, S., Zwirchmayr, J., Steininger, A. (2024). Towards Software-Based Vendor-Independent Preemption for Hardware Accelerated Workloads. In 2024 Austrochip Workshop on Microelectronics (Austrochip). 2024 Austrochip Workshop on Microelectronics (Austrochip), Vienna, Austria. IEEE. Peer-reviewed.
DOI: 10.1109/Austrochip62761.2024.10716010
Steininger, A. (2024). Asynchronous Circuits – Old Iron or Enabler for a New Resilience Level of Digital Circuits? In H. Kubátová, P. Fišer, J. Borecký (Eds.), Proceedings of the 12th Prague Embedded Systems Workshop (pp. 2–2). Czech Technical University.
HDL: 20.500.12708/208721

2023

Tabassam, Z., Steininger, A., Najvirt, R., Huemer, F. (2023). ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. In 2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) (pp. 48–57). IEEE. Peer-reviewed.
DOI: 10.1109/ASYNC58294.2023.10239589
Shehaby, R. E., Függer, M., Steininger, A. (2023). On the Susceptibility of QDI Circuits to Transient Faults. In L. Petrucci J. Sproston (Eds.), Formal Modeling and Analysis of Timed Systems : 21st International Conference, FORMATS 2023, Antwerp, Belgium, September 19–21, 2023, Proceedings (pp. 69–85). Springer LNCS. Peer-reviewed.
DOI: 10.1007/978-3-031-42626-1_5
Tabassam, Z., Steininger, A. (2023). SET Effects on Quasi Delay Insensitive and Synchronous Circuits. In 2023 IEEE European Test Symposium (ETS). Proceedings (pp. 1–6). IEEE. Peer-reviewed.
DOI: 10.34726/5435 / Download: PDF
Tabassam, Z., Steininger, A. (2023). Towards Resilient Quasi Delay Insensitive Conditional Control Elements. In S. Niar, H. Ouarnoughi, A. Skavhaug (Eds.), Proceedings : 26th Euromicro Conference on Digital System Design (DSD 2023), Golem, Durres, Albania, 6-8 September 2023 (pp. 206–213). Peer-reviewed.
DOI: 10.1109/DSD60849.2023.00038

2022

Prabakaran, B. S., Fasching, F., Schreib, J., Steininger, A., Shafique, M. (2022). ATLAS: An IoT Architecture and Secure Open-source Networking Stack for Anonymous Localization and Tracking Using Smartphones and Bluetooth Beacons. arXiv.
DOI: 10.34726/3642 / Download: PDF
Tabassam, Z., Steininger, A. (2022). SET Hardened Derivatives of QDI Buffer Template. In 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Austin, TX, United States of America (the). IEEE. Peer-reviewed.
DOI: 10.34726/3944 / Download: PDF
Elshehaby, R., Steininger, A. (2022). Study and Comparison of QDI Pipeline Components’ Sensitivity to Permanent Faults. In 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Austin, TX, United States of America (the).
DOI: 10.34726/4047 / Download: PDF
Tabassam, Z., Steininger, A. (2022). Towards Resilient QDI Pipeline Implementations. In 2022 25th Euromicro Conference on Digital System Design (DSD) (pp. 657–664). IEEE. Peer-reviewed.
DOI: 10.34726/3942 / Download: PDF
Tabassam, Z., Naqvi, S. R., Steininger, A. (2022). AμFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages. In 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (pp. 32–37). IEEE. Peer-reviewed.
DOI: 10.34726/3941 / Download: PDF
Huemer, F., Najvirt, R., Steininger, A. (2022). On SAT-Based Model Checking of Speed-Independent Circuits. In H. Kubatova (Ed.), 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (pp. 100–105). Institute of Electrical and Electronics Engineers (IEEE). Peer-reviewed.
DOI: 10.1109/DDECS54261.2022.9770165
Colucci, A., Steininger, A., Shafique, M. (2022). enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks. In Proceedings 2022 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS) (pp. 5155–5162).
DOI: 10.1109/IROS47612.2022.9982181

2021

Dür, W., Függer, M., Steininger, A. (2021). Generation of a fault-tolerant clock through redundant crystal oscillators. Microelectronics Reliability, 120, 1–11. Peer-reviewed.
DOI: 10.1016/j.microrel.2021.114088 / Download: PDF
Maier, J., Hartl-Nesic, C., Steininger, A. (2021). Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses. IEEE Transactions on Circuits and Systems I: Regular Papers, 69(3), 1013–1026. Peer-reviewed.
DOI: 10.1109/tcsi.2021.3130349
Elshehaby, R., Steininger, A. (2021). Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines. In 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS). 24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Wien, Austria. Ieee Cs. Peer-reviewed.
DOI: 10.34726/4046 / Download: PDF
Behal, P., Huemer, F. F., Najvirt, R., Steininger, A. (2021). An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. In 2021 24th Euromicro Conference on Digital System Design (DSD). 24th Euromicro Conference on Digital System Design, Palermo, Italy. Peer-reviewed.
DOI: 10.34726/4044 / Download: PDF
Tabassam, Z., Behal, P., Najvirt, R., Steininger, A. (2021). Input/Output-Interlocking for Fault Mitigation in QDI Pipelines. In 2021 Austrochip Workshop on Microelectronics (Austrochip) (pp. 17–20). Peer-reviewed.
DOI: 10.34726/3943 / Download: PDF
Behal, P., Huemer, F., Najvirt, R., Tabassam, Z., Steininger, A. (2021). Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. In 2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) (pp. 25–33). IEEE. Peer-reviewed.
DOI: 10.34726/3945 / Download: PDF
Sekanina, L., Shafique, M., Krstic, M., Steininger, A., Stojanovic, G. (2021). Foreword. In 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 24th International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS 2021), Vienna, Austria. IEEE.
DOI: 10.1109/ddecs52668.2021.9417019

2020

Duer, W., Steininger, A. (2020). Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock. In 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS). 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Novi Sad, Serbia. Ieee Cs. Peer-reviewed.
DOI: 10.1109/ddecs50862.2020.9095577
Brunvand, E., Stevens, K., Moreira, M., Steininger, A. (2020). Welcome Message: ASYNC 2020. In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2020), Salt Lake City, United States of America (the). IEEE Computer Society.
DOI: 10.1109/async49171.2020.00005
Huemer, F. F., Steininger, A. (2020). Timing Domain Crossing using Muller Pipelines. In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 26th IEEE International Symposium on Asynchronous Circuits and Systems, Snowbird, Utah, USA, Austria. Ieee Cs. Peer-reviewed.
DOI: 10.34726/4041 / Download: PDF
Huemer, F. F., Steininger, A. (2020). Sorting Network based Full Adders for QDI Circuits. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. Peer-reviewed.
DOI: 10.34726/4042 / Download: PDF
Huemer, F. F., Najvirt, R., Steininger, A. (2020). Identification and Confinement of Fault Sensitivity Windows in QDI Logic. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. Peer-reviewed.
DOI: 10.34726/4043 / Download: PDF
Elshehaby, R., Steininger, A. (2020). On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective. In 2020 IEEE 38th International Conference on Computer Design (ICCD). IEEE International Conference on Computer Design, Hartford, Connecticut, USA, Austria. Peer-reviewed.
DOI: 10.34726/4045 / Download: PDF

2019

Polzer, T., Huemer, F., Steininger, A. (2019). An Experimental Study of Metastability-Induced Glitching Behavior. Journal of Circuits, Systems, and Computers, 28(supp01), 1940006. Peer-reviewed.
DOI: 10.1142/s0218126619400061
Krstic, M., Jones, I., Steininger, A., Függer, M. (2019). Special Issue “Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018.” Journal of Low Power Electronics and Applications, 9(2), 2.
HDL: 20.500.12708/143834
Huemer, F., Steininger, A. (2019). Novel Approaches for Efficient Delay-Insensitive Communication. Journal of Low Power Electronics and Applications, 9(2), 16. Peer-reviewed.
DOI: 10.3390/jlpea9020016
Maier, J., Steininger, A. (2019). Efficient Metastability Characterization for Schmitt-Triggers. In 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 25th IEEE International Symposium on Asynchronous Circuits and Systems, Hirosaki, Japan.
DOI: 10.1109/ASYNC.2019.00024 / Download: PDF
Paverd, A., Völp, M., Brasser, F., Schunter, M., Asokan, N., Sadeghi, A.-R., Esteves-Verissimo, P., Steininger, A., Holz, T. (2019). Sustainable Security Safety: Challenges and Opportunities. In M. Asplund M. Paulitsch (Eds.), Proceedings 4th International Workshop on Security and Dependability of Critical Embedded Real-Time Systems (CERTS 2019) (p. 13). Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik. Peer-reviewed.
DOI: 10.4230/OASIcs.CERTS.2019.4 / Project: Intel CARS
Steininger, A., Schwendinger, M. (2019). A Systematic Approach to Clock Failure Detection. In 2019 Austrochip Workshop on Microelectronics (Austrochip). Austrochip Workshop on Microelectronics, Wien, Austria. Peer-reviewed.
DOI: 10.1109/austrochip.2019.00018 / Project: Intel CARS

2018

Polzer, T., Huemer, F., Steininger, A. (2018). Refined Metastability Characterization Using a Time-to-Digital Converter. Microelectronics Reliability, 80, 91–99. Peer-reviewed.
DOI: 10.1016/j.microrel.2017.11.017
Huemer, F., Polzer, T., Steininger, A. (2018). Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. In 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE CS Press, Austria. IEEE Xplore Digital Library. Peer-reviewed.
DOI: 10.1109/ddecs.2018.00032
Schütz, M., Steininger, A., Huemer, F., Lechner, J. (2018). State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. In 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE CS Press, Austria. IEEE Xplore Digital Library. Peer-reviewed.
DOI: 10.1109/dft.2018.8602984 / Project: Intel CARS
Huemer, F., Steininger, A. (2018). Advanced Delay-Insensitive 4-Phase Protocols. In 2018 Austrochip Workshop on Microelectronics (Austrochip). IEEE CS Press, Austria. IEEE Xplore Digital Library. Peer-reviewed.
DOI: 10.1109/austrochip.2018.8520702
Huemer, F., Steininger, A. (2018). Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. In 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE CS Press, Austria. IEEE Xplore Digital Library. Peer-reviewed.
DOI: 10.1109/async.2018.00014

2017

Steininger, A., Pawlak, A., Stopjakova, V. (2017). Foreword. Journal of Circuits, Systems, and Computers, 26(08), Article 1702001.
DOI: 10.1142/s0218126617020017
Polzer, T., Steininger, A. (2017). A Model for the Metastability Delay of Sequential Elements. Journal of Circuits, Systems, and Computers, 26(08), 1740010. Peer-reviewed.
DOI: 10.1142/s0218126617400102
Savulimedu Veeravalli, V., Steininger, A., Schmid, U. (2017). A versatile architecture for long-term monitoring of single-event transient durations. Microprocessors and Microsystems, 53, 130–144. Peer-reviewed.
DOI: 10.1016/j.micpro.2017.07.007
Najvirt, R., Polzer, T., Steininger, A. (2017). Measuring Metastability with Free-Running Clocks. In 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017), San Diego, California, United States of America (the). IEEE Computer Society. Peer-reviewed.
DOI: 10.1109/async.2017.18
Polzer, T., Huemer, F., Steininger, A. (2017). Measuring metastability using a time-to-digital converter. In 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Dresden, Germany. IEEE Service Center. Peer-reviewed.
DOI: 10.1109/ddecs.2017.7934582
Andjelkovic, M., Krstic, M., Kraemer, R., Veeravalli, V. S., Steininger, A. (2017). A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. In Proceedings of the 26th IEEE Asian Test Symposium (ATS´17) (pp. 1–6). Peer-reviewed.
HDL: 20.500.12708/57265
Fritz, B., Veeravalli, V. S., Steininger, A., Simek, V. (2017). Setup for an Experimental Study of Radiation Effects in 65nm CMOS. In 2017 Euromicro Conference on Digital System Design (DSD). 20th Euromicro Conference on Digital System Design, Wien, Austria. Peer-reviewed.
DOI: 10.1109/dsd.2017.60

2016

Huemer, F., Lechner, J., Steininger, A. (2016). A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes. In Proceedings 2016 IEEE International Conference on Computer Design (pp. 392–395). Peer-reviewed.
HDL: 20.500.12708/56881
Polzer, T., Huemer, F., Steininger, A. (2016). A Programmable Delay Line for Metastability Characterization in FPGAs. In Proceedings 24th Austrian Workshop on Microelectronics (p. 6). Peer-reviewed.
HDL: 20.500.12708/56883
Veeravalli, V. S., Steininger, A. (2016). Design and Physical Implementation of a Target ASIC for SET Experiments. In Proc. 2016 Euromicro Conference on Digital System Design (DSD) (pp. 694–697). IEEE. Peer-reviewed.
HDL: 20.500.12708/56884 / Project: EASET
Veeravalli, V. S., Steininger, A. (2016). Study of a Delayed Single-Event Effect in the Muller C-element. In Proc 21st IEEE European Test Symposium. 21st IEEE European Test Symposium, Amsterdam, Netherlands (the). Peer-reviewed.
HDL: 20.500.12708/56885 / Project: EASET
Polzer, T., Steininger, A. (2016). A General Approach for Comparing Metastable Behavior of Digital CMOS Gates. In Proc 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (p. 6). Peer-reviewed.
HDL: 20.500.12708/56886
Steininger, A. (2016). Fifty Shades of Synchrony. In A. Mokhov (Ed.), This Asynchronous Woirld (pp. 294–300). Newcastle University.
HDL: 20.500.12708/29323
Steininger, A., Maier, J., Najvirt, R. (2016). The Metastable Behavior of a Schmitt-Trigger. In 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), Porto Alegre, Brazil. IEEE.
DOI: 10.1109/ASYNC.2016.19 / Download: PDF
Steininger, A., Najvirt, R., Maier, J. (2016). Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? In 2016 Euromicro Conference on Digital System Design (DSD). 2016 Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus. IEEE.
DOI: 10.1109/DSD.2016.56 / Download: PDF

2015

Polzer, T., Najvirt, R., Beck, F., Steininger, A. (2015). On the Appropriate Handling of Metastable Voltages in FPGAs. Journal of Circuits, Systems, and Computers, 25(03), 1640020. Peer-reviewed.
DOI: 10.1142/s021812661640020x
Dolev, D., Függer, M., Lenzen, C., Schmid, U., Steininger, A. (2015). Fault-tolerant Distributed Systems in Hardware. European Association for Theoretical Computer Science. Bulletin, 2(116), 43. Peer-reviewed.
HDL: 20.500.12708/151760
Steininger, A., Zimmermann, H., Jantsch, A., Hofbauer, M., Schmid, U., Schweiger, K., Savulimedu Veeravalli, V. (2015). Building reliable systems-on-chip in nanoscale technologies. Elektrotechnik Und Informationstechnik : E i, 132(6), 301–306. Peer-reviewed.
DOI: 10.1007/s00502-015-0319-0
Resch, S., Steininger, A., Scherrer, C. (2015). A Composable Real-Time Architecture for Replicated Railway Applications. Journal of Systems Architecture, 61(9), 472–485. Peer-reviewed.
DOI: 10.1016/j.sysarc.2015.04.003
Veeravalli, V. S., Steininger, A. (2015). Can we trust SET Injection Models? In MEDIAN Finale Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (p. 6). Peer-reviewed.
HDL: 20.500.12708/56359
Najvirt, R., Steininger, A. (2015). A Versatile and Reliable Glitch Filter for Clocks. In 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (p. 8). Peer-reviewed.
HDL: 20.500.12708/56360
Lechner, J., Steininger, A., Huemer, F. (2015). Methods for Analysing and Improving the Fault Resilience of Delay-Insensitive Codes. In 33rd IEEE International Conference on Computer Design (p. 8). Peer-reviewed.
HDL: 20.500.12708/56358
Najvirt, R., Steininger, A. (2015). A Pausible Clock with Crystal Oscillator Accuracy. In 22nd European Conference on Circuit Theory and Design (p. 4). Peer-reviewed.
HDL: 20.500.12708/56356
Veeravalli, V. S., Steininger, A. (2015). Reliable and Continuous Measurement of SET Pulse Widths. In 18th Euromicro Conference on Digital System Design (p. 8). Peer-reviewed.
HDL: 20.500.12708/56354
Polzer, T., Steininger, A. (2015). Enhanced Metastability Characterization based on AC Analysis. In 18th Euromicro Conference on Digital System Design (p. 9). Peer-reviewed.
HDL: 20.500.12708/56353
Polzer, T., Steininger, A. (2015). Measuring the Distribution of Metastable Upsets over Time. In Measuring the Distribution of Metastable Upsets over Time (p. 8). Peer-reviewed.
HDL: 20.500.12708/56352
Najvirt, R., Polzer, T., Beck, F., Steininger, A. (2015). Containment of Metastable Voltages in FPGAs. In 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (p. 6). Peer-reviewed.
HDL: 20.500.12708/56351
Huemer, F., Schütz, M., Steininger, A. (2015). Revisiting Sorting Network based Completion Detection for 4 Phase Delay Insensitive Codes. In Austrochip Workshop on Microelectronics (p. 6). Peer-reviewed.
HDL: 20.500.12708/56350
Schütz, M., Huemer, F., Steininger, A. (2015). A Practical Comparison of 2-Phase Delay Insensitve Communication Protocols. In Austrochip Workshop on Microelectronics (p. 6). Peer-reviewed.
HDL: 20.500.12708/56349
Najvirt, R., Steininger, A. (2015). How to Synchronize a Pausible Clock to a Reference. In 21st IEEE International Symposium on Asynchronous Circuits and Systems (p. 8). Peer-reviewed.
HDL: 20.500.12708/56348

2014

Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., Kowalewski, S. (2014). Runtime verification of microcontroller binary code. Science of Computer Programming, 80, 109–129. Peer-reviewed.
DOI: 10.1016/j.scico.2012.10.015
Dolev, D., Függer, M., Posch, M., Schmid, U., Steininger, A., Lenzen, C. (2014). Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip. Journal of Computer and System Sciences, 80(4), 860–900. Peer-reviewed.
DOI: 10.1016/j.jcss.2014.01.001
Maier, J., Steininger, A. (2014). Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic. In 17th International Symposium on Design and Diagnostics of Electronic Circuits Systems (pp. 33–38). Institute of Electrical and Electronics Engineers (IEEE).
DOI: 10.1109/DDECS.2014.6868759 / Download: PDF
Naqvi, S. R., Lechner, J., Steininger, A. (2014). Protection of Muller-Pipelines from transient faults. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium Exhibit on Quality Electronic Design, Santa Clara, United States of America (the). Peer-reviewed.
DOI: 10.1109/isqed.2014.6783315
Veeravalli, V. S., Steininger, A., Schmid, U. (2014). Measuring SET pulsewidths in logic gates using digital infrastructure. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium Exhibit on Quality Electronic Design, Santa Clara, United States of America (the). Peer-reviewed.
DOI: 10.1109/isqed.2014.6783331
Veeravalli, V. S., Steininger, A. (2014). Architecture for monitoring SET propagation in 16-bit Sklansky adder. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium Exhibit on Quality Electronic Design, Santa Clara, United States of America (the). Peer-reviewed.
DOI: 10.1109/isqed.2014.6783354
Veeravalli, V. S., Steininger, A. (2014). Diagnosis of SET Propagation in Combinational Logic under Dynamic Operation. In Proceedings 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10) (p. 6). Peer-reviewed.
HDL: 20.500.12708/55130
Anghel, L., Veeravalli, V. S., Alexandrescu, D., Steininger, A., Schneider, K., Costenaro, E. (2014). Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum. In Proceedings 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10) (p. 6). Peer-reviewed.
HDL: 20.500.12708/55131
Naqvi, S. R., Steininger, A. (2014). A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments. In Proceedings Design Automation &Test in Europe (p. 6). Peer-reviewed.
HDL: 20.500.12708/55132
Steininger, A., Veeravalli, V. S., Alexandrescu, D., Costenaro, E., Anghel, L. (2014). Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. In 2014 IEEE 32nd International Conference on Computer Design (ICCD). 2014 32nd IEEE International Conference on Computer Design (ICCD), Seoul, Korea (the Republic of). IEEE. Peer-reviewed.
DOI: 10.1109/iccd.2014.6974663 / Project: EASET
Najvirt, R., Steininger, A. (2014). Equivalence of clock gating and synchronization with applicability to GALS communication. In 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, Isles Balears, Spain. IEEE. Peer-reviewed.
DOI: 10.1109/patmos.2014.6951873
Veeravalli, V. S., Steininger, A. (2014). Long term on-chip monitoring of SET pulsewidths in a fully digital ASIC. In 22nd Austrian Workshop on Microelectronics (Austrochip). 22nd Austrian Workshop on Microelectronics, Graz, Austria. IEEE. Peer-reviewed.
DOI: 10.1109/austrochip.2014.6946318 / Project: EASET

2013

Veeravalli, V. S., Polzer, T., Schmid, U., Steininger, A., Hofbauer, M., Schweiger, K., Dietrich, H., Schneider-Hornstein, K., Zimmermann, H., Voss, K.-O., Merk, B., Hajek, M. (2013). An infrastructure for accurate characterization of single-event transients in digital circuits. Microprocessors and Microsystems, 37, 772–791. Peer-reviewed.
HDL: 20.500.12708/156041
Hofbauer, M., Schweiger, K., Zimmermann, H., Giesen, U., Langner, F., Schmid, U., Steininger, A. (2013). Supply Voltage Dependent On-Chip Single-Event Transient Pulse Shape Measurements in 90-nm Bulk CMOS Under Alpha Irradiation. IEEE Transactions on Nuclear Science, 60(4), 2640–2646. Peer-reviewed.
HDL: 20.500.12708/156043
Naqvi, S. R., Najvirt, R., Steininger, A. (2013). A Multi-Credit Flow Control Scheme for Asynchronous NoCs. In Proc. 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (p. 6). Peer-reviewed.
HDL: 20.500.12708/55006
Najvirt, R., Naqvi, S. R., Steininger, A. (2013). Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs. In Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on (p. 9). Peer-reviewed.
HDL: 20.500.12708/55005
Veeravalli, V. S., Steininger, A. (2013). Performance of Radiation Hardening Techniques under Voltage and Temperature Variations. In Proc. 2013 IEEE Aerospace Conference (p. 6). Peer-reviewed.
HDL: 20.500.12708/55004
Najvirt, R., Veeravalli, V. S., Steininger, A. (2013). Particle Strikes in C-Gates: Relevance of SET Shapes. In Proceedings of the MEDIAN Workshop 2013 (p. 4). Peer-reviewed.
HDL: 20.500.12708/55003
Resch, S., Steininger, A., Scherrer, C. (2013). Software Composability and Mixed Criticality for Triple Modular Redundant Architectures. In Proceedings of the 2013 SASSUR Workshop (p. 4). Peer-reviewed.
HDL: 20.500.12708/55002
Naqvi, S. R., Steininger, A., Lechner, J. (2013). An SET Tolerant Tree Arbiter Cell. In Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on (p. 9). Peer-reviewed.
HDL: 20.500.12708/55001
Polzer, T., Steininger, A. (2013). SET Propagation in Micropipelines. In 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013) (p. 8). Peer-reviewed.
HDL: 20.500.12708/54998
Polzer, T., Steininger, A. (2013). Digital Late-Transition Metastability Simulation Model. In Proceedings of the 16th Euromicro Conference on Digital System Design (p. 8). Peer-reviewed.
HDL: 20.500.12708/55024
Polzer, T., Steininger, A. (2013). Metastability Characterization for Muller C-Elements. In 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013) (p. 8). Peer-reviewed.
HDL: 20.500.12708/55023
Polzer, T., Steininger, A. (2013). An Approach for Efficient Metastability Characterization of FPGAs through the Designer. In 19th IEEE International Symposium on Asynchronous Circuits and Systems (p. 9). Peer-reviewed.
HDL: 20.500.12708/55021
Polzer, T., Steininger, A., Lechner, J. (2013). Muller C-Element Metastability Containment. In Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (pp. 103–112). Lecture Notes in Computer Science. Peer-reviewed.
HDL: 20.500.12708/54509

2012

Hofbauer, M., Schweiger, K., Dietrich, H., Zimmermann, H., Voss, K.-O., Merk, B., Schmid, U., Steininger, A. (2012). Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating Through a 90 nm Bulk CMOS Inverter Chain. IEEE Transactions on Nuclear Science, 59(6), 2778–2784. Peer-reviewed.
DOI: 10.1109/tns.2012.2223233
Naqvi, S. R., Veeravalli, V. S., Steininger, A. (2012). Protecting an Asynchronous NoC against Transient Channel Faults. In Proc. of 15th Euromicro Conference on Digital System Design (p. 8). Peer-reviewed.
HDL: 20.500.12708/54503
Hofbauer, M., Schweiger, K., Zimmermann, H., Giesen, U., Langner, F., Schmid, U., Steininger, A. (2012). Supply Voltage Dependent On-chip Single Event Transient Pulse Shape Measurements in 90 nm Bulk CMOS under Alpha Irradiation. In Proceedings 21st European Conference on Radiation and its Effects on Components and Systems (RADECS’12). 21st European Conference on Radiation and its Effects on Components and Systems (RADECS’12), Biarritz, France. Peer-reviewed.
HDL: 20.500.12708/54565
Veeravalli, V. S., Steininger, A., Schmid, U., Polzer, T. (2012). Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. In Proceedings 15th Euromicro Symposium on Digital System Design: Architectures, Methods and Tools (DSD’12) (pp. 8–17). Peer-reviewed.
HDL: 20.500.12708/54564
Reinbacher, T., Horauer, M., Steininger, A. (2012). A Runtime Verification Unit for Microcontrollers. In System, Software, SoC and Silicon Debug Conference (S4D), 2012 (pp. 1–6). Peer-reviewed.
HDL: 20.500.12708/54566 / Project: CEVTES
Reinbacher, T., Geist, J., Moosbrugger, P., Horauer, M., Steininger, A. (2012). Parallel Runtime Verification of Temporal Properties for Embedded Software. In Mechatronics and Embedded Systems and Applications (MESA), 2012 IEEE/ASME International Conference on (pp. 224–231). Peer-reviewed.
HDL: 20.500.12708/54567 / Project: CEVTES
Veeravalli, V. S., Steininger, A. (2012). Monitoring Single Event Transient Effects in Dynamic Mode. In 1st Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2012) (pp. 51–54). Peer-reviewed.
HDL: 20.500.12708/54568
Veeravalli, V. S., Steininger, A. (2012). Radiation-Tolerant Combinational Gates - An Implementation Based Comparison. In Design and Diagnostics of Electronic Circuits Systems (DDECS), 2012 IEEE 15th International Symposium on (pp. 115–120). Peer-reviewed.
HDL: 20.500.12708/54570
Fritz, B., Veeravalli, V. S., Steininger, A. (2012). Reliable Gateway for Radiation Experiments on a VLSI Chip. In Austrochip 2012 (pp. 65–70). Peer-reviewed.
HDL: 20.500.12708/54571
Veeravalli, V. S., Steininger, A. (2012). LFSR Implementation Using C-Elements. In MEMICS 2012 (pp. 73–83). Peer-reviewed.
HDL: 20.500.12708/54572
Veeravalli, V. S., Steininger, A. (2012). Efficient Radiation-Hardening of a Muller C-Element. In 2012 Single Event Effects Symposium. 2012 Single Event Effects Symposium (SEE 2012), San Diego, United States of America (the). Peer-reviewed.
HDL: 20.500.12708/54573
Milbredt, P., Glass, M., Lukasiewycz, M., Steininger, A., Teich, J. (2012). Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach. In Design, Automation Test in Europe Conference Exhibition (DATE 2012) Proceedings (pp. 276–279). EDAA. Peer-reviewed.
HDL: 20.500.12708/54574

2011

Steininger, A., Tummeltshammer, P. (2011). Replicated processors on a single die - How independently do they fail? Elektrotechnik Und Informationstechnik : E i, 128(6), 245–250. Peer-reviewed.
DOI: 10.1007/s00502-011-0005-9
Fuchs, G., Steininger, A. (2011). VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation. Journal of Electrical and Computer Engineering, 2011. Peer-reviewed.
DOI: 10.1155/2011/936712 / Project: DARTS
Reinbacher, T., Steininger, A., Müller, T., Horauer, M., Brauer, J., Kowalewski, S. (2011). Hardware support for efficient testing of embedded software. In International Conference on Mechatronic and Embedded Systems and Applications. The 7th ASME/IEEE International Conference on Mechatronic and Embedded Systems and Applications, Washington, United States of America (the). ASME. Peer-reviewed.
HDL: 20.500.12708/54082 / Project: CEVTES
Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., Kowalewski, S. (2011). Past Time LTL Runtime Verification for Microcontroller Binary Code. In Formal Methods for Industrial Critical Systems (pp. 37–51). Springer Berlin / Heidelberg. Peer-reviewed.
DOI: 10.1007/978-3-642-24431-5_5 / Project: CEVTES
Reinbacher, T., Brauer, J., Schachinger, D., Steininger, A., Kowalewski, S. (2011). Automated test-trace inspection for microcontroller binary code. In Runtime Verification (pp. 239–244). Peer-reviewed.
HDL: 20.500.12708/54078 / Project: CEVTES

2010

Friesenbichler, W., Panhofer, T., Steininger, A. (2010). A deterministic approach for hardware fault injection in asynchronous QDI logic. In 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria, Austria. IEEE. Peer-reviewed.
DOI: 10.1109/ddecs.2010.5491758
Friesenbichler, W., Panhofer, T., Steininger, A. (2010). Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm. In 2010 International Conference on Dependable Systems and Networks Workshops (DSN-W). WSDN 2010 (4th Workshop on Dependable and Secure Nanocomputing, Chicago, United States of America (the). IEEE Computer Socitey. Peer-reviewed.
DOI: 10.1109/dsnw.2010.5542609
Friesenbichler, W., Panhofer, T., Steininger, A. (2010). Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study. In 2010 NASA/ESA Conference on Adaptive Hardware and Systems. NASA/ESA 2010 (Conference on Adaptive Hardware and Systems), Anaheim, United States of America (the). IEEE Computer Society. Peer-reviewed.
DOI: 10.1109/ahs.2010.5546277
Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., Kowalewski, S. (2010). Test-Case Generation for Embedded Binary Code Using Abstract Interpretation. In MEMICS proceedings (pp. 151–158). Peer-reviewed.
HDL: 20.500.12708/53554 / Project: CEVTES
Jeitler, M., Lechner, J., Steininger, A. (2010). Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. In 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria, Austria. IEEE Computer Society. Peer-reviewed.
DOI: 10.1109/ddecs.2010.5491776

2009

Tummeltshammer, P., Steininger, A. (2009). On the role of the power supply as an entry for common cause faults—An experimental analysis. In 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. DDECS 2009 (Design and Diagnostics of Electronic Circuits and Systems), Liberec, Czechia. IEEE. Peer-reviewed.
DOI: 10.1109/ddecs.2009.5012118
Polzer, T., Handl, T., Steininger, A. (2009). A Metastability-Free Multi-synchronous Communication Scheme for SoCs. In R. Guerraoui F. Petit (Eds.), Stabilization, Safety, and Security of Distributed Systems: 11th International Symposium, SSS 2009, Lyon, France, November 3-6, 2009. Proceedings (pp. 578–592). Springer. Peer-reviewed.
DOI: 10.1007/978-3-642-05118-0_40 / Project: DARTS
Tummeltshammer, P., Steininger, A. (2009). Power Supply Induced Common Cause Faults - Experimental Assessment of Potential Countermeasures. In DSN 2009 - Full Program (pp. 449–457). Springer. Peer-reviewed.
HDL: 20.500.12708/52864
Fuchs, G., Függer, M., Steininger, A. (2009). On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme. In 2009 15th IEEE Symposium on Asynchronous Circuits and Systems. ASYNC 2009 (International Symposium on Asynchronous Circuits and Systems), Chapel Hill, United States of America (the). IEEE Computer Society. Peer-reviewed.
DOI: 10.1109/async.2009.15 / Project: DARTS
Függer, M., Fuchs, G., Steininger, A. (2009). On the Stability and Robustness of Non-Synchronous Circuits with Timing Loops. In WSDN 2009 (pp. 45–50). Springer. Peer-reviewed.
HDL: 20.500.12708/52868 / Project: DARTS
Friesenbichler, W., Steininger, A. (2009). Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic. In 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools. DSD 2009 (Euromicro Conference on Digital System Design), Patras, Greece. IEEE Computer Society. Peer-reviewed.
DOI: 10.1109/dsd.2009.142
Tummeltshammer, P., Steininger, A. (2009). On the Risk of Fault Coupling over the Chip Substrate. In 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools. DSD 2009 (Euromicro Conference on Digital System Design), Patras, Greece. IEEE Computer Society. Peer-reviewed.
DOI: 10.1109/dsd.2009.185
Armengaud, E., Steininger, A. (2009). Remote Measurement of Local Oscillator Drifts in FlexRay Networks. In DATE09 (pp. 1082–1087). Springer. Peer-reviewed.
HDL: 20.500.12708/52872 / Project: EXTRACT
Steininger, A. (2009). Error Containment in the Presence of Metastability. In Fault-Tolerant Distributed Algorithms on VLSI Chips (p. ?). Leibniz Zentrum Informatik. Peer-reviewed.
HDL: 20.500.12708/52873
Rahbaran, B., Steininger, A. (2009). Is Asynchronous Logic More Robust Than Synchronous Logic? IEEE Transactions on Dependable and Secure Computing, 6(4), 282–294. Peer-reviewed.
DOI: 10.1109/tdsc.2008.37
Függer, M., Steininger, A., Armengaud, E. (2009). Safely Stimulating the Clock Synchronization Algorithm in Time-Triggered Systems - A Combined Formal and Experimental Approach. IEEE Transactions on Industrial Informatics, 5(2), 132–145. Peer-reviewed.
HDL: 20.500.12708/166191 / Project: EXTRACT

2008

Armengaud, E., Steininger, A., Horauer, M. (2008). Towards a Systematic Test for Embedded Automotive Communication Systems. IEEE Transactions on Industrial Informatics, 4(3), 146–155. Peer-reviewed.
DOI: 10.1109/TII.2008.2002704 / Project: STEACS
Grahsl, J., Handl, T., Steininger, A. (2008). Exploring the Usefulness of the Gate-level Stuck-at Fault Model for Muller C-Elements. In 20. Workshop Testmethoden und Vuverlässigkeit von Schaltungen und Systemen (pp. 165–169). Peer-reviewed.
HDL: 20.500.12708/52459 / Project: DARTS
Milbredt, P., Horauer, M., Steininger, A. (2008). An investigation of the clique problem in FlexRay. In 2008 International Symposium on Industrial Embedded Systems. SIES´2008 Third international symposium on industrial embedded systems, Montpellier - La Grande Motte, France, EU. Peer-reviewed.
DOI: 10.1109/sies.2008.4577700
Armengaud, E., Függer, M., Steininger, A. (2008). Safe deterministic replay for stimulating the clock synchronization algorithm in time-triggered systems. In 2008 IEEE International Workshop on Factory Communication Systems. WFCS, Turin, Italy. Peer-reviewed.
DOI: 10.1109/wfcs.2008.4638707 / Project: EXTRACT
Milbredt, P., Steininger, A., Horauer, M. (2008). Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks. In 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008). IEEE International Workshop on Electronic Design, Test and Applications, Hong-Kong, Non-EU. Peer-reviewed.
DOI: 10.1109/delta.2008.74
Ambrosch, K., Humenberger, M., Kubinger, W., Steininger, A. (2008). Extending two non-parametric transforms for FPGA based stereo matching using bayer filtered cameras. In 2008 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops. IEEE Conference on Computer Vision and Pattern Recognition, 2008. CVPR ’08, Anchorage, Alaska, USA, Non-EU. Peer-reviewed.
DOI: 10.1109/cvprw.2008.4563146
Forster, W., Kutschera, C., Steininger, A., Göschka, K. M. (2008). Automated Generation of Explicit Connectors for Component Based Hardware/Software Interaction in Embedded Real-Time Systems. In Proceedings of the 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS 2008), (IPDPS 2008) (pp. 1–8). IEEE Computer Society. Peer-reviewed.
HDL: 20.500.12708/52268
Fuchs, G., Függer, M., Schmid, U., Steininger, A. (2008). Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip. In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. 11th EUROMICRO Conference on Digital System Design (DSD 2008), Parma, Italien, EU. IEEE. Peer-reviewed.
DOI: 10.1109/dsd.2008.65 / Project: DARTS

2007

Schmid, U., Steininger, A., Sust, M. (2007). FIT-IT Projekt DARTS: Dezentrale fehlertolerante Taktgenerierung. Elektrotechnik und Informationstechnik : e i, 124(1–2), 3–8. Peer-reviewed.
DOI: 10.1007/s00502-006-0409-0
Handl, T., Steininger, A., Kempf, G. (2007). An Efficient Test Strategy for a Fault-Tolerant Clock Generator for Systems-on-Chip. In 19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (pp. 66–70). Peer-reviewed.
HDL: 20.500.12708/51796 / Project: DARTS
Kottke, T., Steininger, A. (2007). Vergleich zweier zwischen Sicherheit und Performanz rekonfigurierbarer Prozessorsysteme. In 19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen. 19. ITG/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Errlangen, EU. Peer-reviewed.
HDL: 20.500.12708/51797
Schmid, U., Steininger, A., Veith, H. (2007). Towards a Systematic Design of Fault-Tolerant Asynchronous Circuits. In Fachtagung Zuverlässigkeit und Entwurf (pp. 173–174). VDE Verlag. Peer-reviewed.
HDL: 20.500.12708/51805
Grahsl, J., Handl, T., Steininger, A., Kempf, G. (2007). SAFE - A Scalable Environment for Automated Transistor Level Fault Effect Analysis. In Austrochip - Workshop on Microelectronics (pp. 91–98). Peer-reviewed.
HDL: 20.500.12708/52053 / Project: DARTS
Handl, T., Steininger, A., Kempf, G. (2007). Adopting the Scan Approach for a Fault Tolerant Asynchronous Clock Generation Circuit. In Proceedings IDT’07 - The Second International Design and Test Workshop (pp. 115–119). Peer-reviewed.
HDL: 20.500.12708/52055 / Project: DARTS
Armengaud, E., Steininger, A., Hanzlik, A. (2007). The Effect of Quartz Drift on Convergence-Average based Clock Synchronization. In Proceedings of the 12th IEEE Conference on Emerging Technologies and Factory Automation (pp. 1123–1130). Peer-reviewed.
HDL: 20.500.12708/52061 / Project: EXTRACT
Kottke, T., Steininger, A. (2007). A Fail-Silent Reconfigurable Superscalar Processor. In 13th Pacific Rim International Symposium on Dependable Computing (PRDC’07), Melbourne (pp. 232–239). Peer-reviewed.
HDL: 20.500.12708/52063
Horauer, M., Armengaud, E., Steininger, A. (2007). Concepts and Tools for the Test of the Communication Sub-System of Time-Triggered Distributed Embedded Systems. In ASME 2007 International Conference on Design Engineering Technical Conferences Computers and Information in Engineering. International Conference on Design Engineering Technical Conferences Computers and Information in Engineering (ASME), Las Vegas, Non-EU. Peer-reviewed.
HDL: 20.500.12708/52064 / Project: STEACS
Ambrosch, K., Humenberger, M., Kubinger, W., Steininger, A. (2007). Hardware Implementation of an SAD based stereo vision algorithm. In Proceedings of Third IEEE Workshop on Embedded Computer Vision. Third IEEE Workshop on Embedded Computer Vision, Minneapolis, Non-EU. Peer-reviewed.
HDL: 20.500.12708/52065

2006

El Salloum, C., Steininger, A., Tummeltshammer, P. (2006). Recovery Mechanisms for Dual Core Architectures. In 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006, Proceedings (pp. 380–388). Peer-reviewed.
HDL: 20.500.12708/51601
Delvai, M., Steininger, A. (2006). Teaching Hardware Software Codesign to Software Engineers. In International Workshop on Reconfigurable Computing Education. 1st International Workshop on Reconfigurable Computing Education, Karlsruhe, EU. Peer-reviewed.
HDL: 20.500.12708/51473
Steininger, A., Kottke, T. (2006). Ein dynamisch rekonfigurierbarer superskalarer Prozessor mit den Modi Sicherheit und Performanz. In 18. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (pp. 36–40). Peer-reviewed.
HDL: 20.500.12708/51501
Kottke, T., Steininger, A. (2006). A Reconfigurable Generic Dual-Core Architecture. In Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN) (pp. 45–54). Peer-reviewed.
HDL: 20.500.12708/51502
Fuchs, G., Függer, M., Steininger, A., Zangerl, F. (2006). Analysis of Constraints in a Fault-Tolerant Distributed Clock Generation Scheme. In WDES 2006 3rd Workshop on Dependable Embedded Systems (pp. 22–27). Peer-reviewed.
HDL: 20.500.12708/51503 / Project: DARTS
Steininger, A., Handl, T., Fuchs, G., Zangerl, F. (2006). Testing the Hardware Implementation of a Distributed Clock Generation Algorithm for SoCs. In East-West Design Test International Workshop (pp. 59–64). Peer-reviewed.
HDL: 20.500.12708/51504 / Project: DARTS
Függer, M., Handl, T., Steininger, A., Widder, J., Tögel, C. (2006). An Efficient Test for a Transition Signalling based Up-/Down-Counter. In Austrochip Mikroelektroniktagung (pp. 55–62). Peer-reviewed.
HDL: 20.500.12708/51505 / Project: DARTS
Fuchs, G., Grahsl, J., Schmid, U., Steininger, A., Kempf, G. (2006). Threshold Modules -- Die Schlüsselelemente zur Verteilten Generierung eines Fehlertoleranten Taktes. In Austrochip Mikroelektroniktagung (pp. 149–156). Peer-reviewed.
HDL: 20.500.12708/51506 / Project: DARTS
Steininger, A., Függer, M., Schmid, U., Fuchs, G. (2006). Fault-Tolerant Algorithms on SoCs - A case study. In Supplement Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN) (pp. 190–191). Peer-reviewed.
HDL: 20.500.12708/51508 / Project: DARTS
Ferringer, M., Fuchs, G., Steininger, A., Kempf, G. (2006). VLSI Implementation of a Fault-Tolerant Distributed Clock Generation. In The 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (pp. 563–571). Peer-reviewed.
HDL: 20.500.12708/51509 / Project: DARTS
Armengaud, E., Steininger, A. (2006). A Remote and Transparent Approach for the Test and Diagnosis of Automotive Networks. In Junior Scientist Conference 2006. Junior Scientist Conference, Wien, Austria. Peer-reviewed.
HDL: 20.500.12708/51516 / Project: EXTRACT
Armengaud, E., Steininger, A. (2006). Pushing the Limits of Remote Online Diagnosis in FlexRay Networks. In 6th IEEE International Workshop on Factory Communication Systems. IEEE International Workshop on Factory Communication Systems, Porto, Portugal. Peer-reviewed.
HDL: 20.500.12708/51517 / Project: EXTRACT
Armengaud, E., Steininger, A., Horauer, M. (2006). Automatic Parameter Identification in FlexRay Based Automotive Communication Networks. In 11th IEEE International Conference on Emerging Technologies and Factory Automation (pp. 897–904). IEEE. Peer-reviewed.
DOI: 10.1109/ETFA.2006.355404 / Projects: STEACS, EXTRACT
Delvai, M., Steininger, A. (2006). Solving the Fundamental Problem of Digital Design -- A Systematic Review of Design Methods. In 9th Euromicro Conference on Digital System Design - Architectures, Methods and Tools (pp. 131–136). Peer-reviewed.
HDL: 20.500.12708/51526
Delvai, M., Steininger, A. (2006). Asynchronous Logic Design - from Concepts to Implementation. In The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications - Volume 1 (pp. 81–86). Peer-reviewed.
HDL: 20.500.12708/51528
Delvai, M., Steininger, A. (2006). A Practical Comparison of Logic Design Styles. In The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications - Volume 3 (pp. 61–66). Peer-reviewed.
HDL: 20.500.12708/51530
Tummeltshammer, P., Steininger, A. (2006). Time-Multiplexed Multiple Constant Multiplication. In Junior Scientist Conference 2006 (pp. 77–78). Peer-reviewed.
HDL: 20.500.12708/51570
Handl, T., Steininger, A. (2006). Implementation of an FPGA-Based Hardware Fault Injector. In Junior Scientist Conference 2006 (pp. 23–24). Peer-reviewed.
HDL: 20.500.12708/51572

2005

Armengaud, E., Steininger, A., Horauer, M. (2005). Efficient Stimulus Genereation for Remote Testing of Distributed Systems - The Flexray Example. In Proceedings of the 10th IEEE Internationla Conference on Emerging Technologies and Factory Automation (pp. 763–770). IEEE. Peer-reviewed.
HDL: 20.500.12708/51082 / Project: STEACS
Kottke, T., Steininger, A. (2005). Designoptimierung eines Prozessors mit Eigenfehlererkennung. In 16. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen; (pp. 55–59). Peer-reviewed.
HDL: 20.500.12708/51133
Delvai, M., Fuchs, G., Handl, T., Huber, W., Steininger, A. (2005). Design of an Asynchronous Microprocessor with Four-State Logic. In Austrochip 2005 (pp. 105–112). Peer-reviewed.
HDL: 20.500.12708/51134
Armengaud, E., Rothensteiner, F., Steininger, A., Pallierer, R., Horauer, M., Zauner, M. (2005). A Structured Approach for the Systematic Test of Embedded Automotive Communication Systems. In Proceedings International Test Conference 2005 (pp. 21–28). IEEE Computer Society. Peer-reviewed.
HDL: 20.500.12708/51142 / Project: STEACS
Pallierer, R., Horauer, M., Zauner, M., Steininger, A., Armengaud, E., Rothensteiner, F. (2005). A Generic Tool for Systematic Tests in Embedded Automotive Communication Systems. In Embedded World 2005. Embedded World 2005, Germany. unbekannt.
HDL: 20.500.12708/51143 / Project: STEACS
Armengaud, E., Steininger, A., Horauer, M. (2005). An Efficient Test and Diagnosis Environment for Communication Controllers. In Austrochip 2005. Austrochip, Graz, Austria, Austria. ??? Peer-reviewed.
HDL: 20.500.12708/51144 / Project: STEACS
Armengaud, E., Rothensteiner, F., Steininger, A., Horauer, M. (2005). A Flexible Hardware Architecture for Fast Access on Large Non-Volatile Memories. In Proceedings of IEEE Workshop on Design Diagnostics of Electronic Circuits Systems (DDECS) 2005 (pp. 113–120). Peer-reviewed.
HDL: 20.500.12708/51172 / Project: STEACS
Armengaud, E., Steininger, A., Horauer, M. (2005). A Method for Bit Level Test and Diagnosis of Communication Services. In Proceedings of IEEE Workshop on Design Diagnostics of Electronic Circuits Systems (DDECS) 2005 (pp. 69–74). Peer-reviewed.
HDL: 20.500.12708/51174 / Project: STEACS
Schmid, U., Kopetz, H., Puschner, P., Mayerhofer, L., Steininger, A., Grünbacher, H., Kastner, W., Krall, A. (2005). Antrag UNI-Infrastruktur III, Embedded Systems Research Cluster.
HDL: 20.500.12708/33035

2004

Fuchs, G., Schmid, U., Steininger, A. (2004). Ein Verfahren für das verteilte Generieren eines fehlertoleranten adaptiven Taktes in Hardware.
HDL: 20.500.12708/32979 / Project: DARTS
Schmid, U., Steininger, A. (2004). Dezentrale Fehlertolerante Taktgenerierung in VLSI Chips.
HDL: 20.500.12708/32988
Steininger, A., Handl, T., Fuchs, G. (2004). EPOCAL - Exploring the Potential of Code Alternation Logic.
HDL: 20.500.12708/32989
Fuchs, G., Schmid, U., Steininger, A. (2004). DARTS - Distributed Algorithms for Robust Tick Synchronization.
HDL: 20.500.12708/32990
Steininger, A., Delvai, M., Huber, W. (2004). Code Alternation Logic -- A Novel and Efficient Method for Delay-Insensitive Asynchronous Circuits.
HDL: 20.500.12708/32991
Huber, W., Steininger, A., Delvai, M. (2004). Delay Insensitive Asychronous Pipeline Implementation for Code Alternation Logic.
HDL: 20.500.12708/32992
Steininger, A., Delvai, M., Huber, W. (2004). Synchronous and Asynchronous Design Methods -- A Hardware Designer’s Perspective.
HDL: 20.500.12708/32993
Steininger, A., Delvai, M., Huber, W. (2004). Code Alternation Logic (CAL): A Novel Efficient Design Approach for Delay-Insensitive Asynchronous Circuits.
HDL: 20.500.12708/32994
Delvai, M., Steininger, A., Huber, W. (2004). Solving the Fundamental Problem of Digital Design -- A Systematic Review of Design Methods.
HDL: 20.500.12708/32995
Armengaud, E., Steininger, A., Horauer, M. (2004). Monitoring and Replay hardware -- Requirements and Concepts.
HDL: 20.500.12708/32996 / Project: STEACS
Armengaud, E., Steininger, A. (2004). Automatic Parameter Detection for Communication Protocols.
HDL: 20.500.12708/32998 / Project: STEACS
Armengaud, E., Steininger, A. (2004). Fault Injection Method.
HDL: 20.500.12708/33001 / Project: STEACS
Armengaud, E., Steininger, A., Horauer, M. (2004). Fault Injection -- Requirements and Concepts.
HDL: 20.500.12708/33002 / Project: STEACS
Armengaud, E., Rothensteiner, F., Steininger, A., Horauer, M. (2004). A Flexible Hardware Architecture for Fast Access on Large Non-Volatile Memories.
HDL: 20.500.12708/33003 / Project: STEACS
Steininger, A., Horauer, M., Armengaud, E. (2004). Options for Remote Diagnosis in Automotive Distributed Networks.
HDL: 20.500.12708/33004 / Project: STEACS
Rahbaran, B., Steininger, A. (2004). A Strategy for Experimental Fault Injection into an Asynchronous Processor.
HDL: 20.500.12708/33005
Kottke, T., Steininger, A. (2004). A Reconfigurable Generic Dual Core Architecture.
HDL: 20.500.12708/33006
El Salloum, C., Steininger, A. (2004). Recovery Mechanisms for Dual Core Architectures.
HDL: 20.500.12708/33007
Tummeltshammer, P., Pueschel, M., Steininger, A., Überhuber, C. W. (2004). Constant Multiplication Methods.
HDL: 20.500.12708/33008
Tummeltshammer, P., Pueschel, M., Steininger, A., Überhuber, C. W. (2004). Face Recognition on ASICs.
HDL: 20.500.12708/33009
Horauer, M., Rothensteiner, F., Zauner, M., Armengaud, E., Steininger, A., Friedl, H., Pallierer, R. (2004). An FPGA based SoC Design for Testing Embedded Automotive Communication Systems employing the FlexRay Protocol. In Austrochip 2004 (pp. 119–123). TU-Wien. Peer-reviewed.
HDL: 20.500.12708/50973 / Project: STEACS

2003

Scherrer, C., Steininger, A. (2003). Dealing With Dormant Faults in an Embedded Fault-Tolerant Computer System. IEEE Transactions on Reliability, 52(4), 512–522. Peer-reviewed.
HDL: 20.500.12708/174825
Thaller, K., Steininger, A. (2003). A Transparent Online Memory Test for Simultaneous Detection of Functional Faults and Soft Errors in Memories. IEEE Transactions on Reliability, 52(4), 413–422. Peer-reviewed.
HDL: 20.500.12708/174824

Presentations

Dolev, D., Függer, M., Hofstätter, M., Lenzen, C., Perner, M., Posch, M., Schmid, U., Sigl, M., Steininger, A. (2013). FATAL+HEX: Fault-Tolerant Self-Stabilizing Clock Generation+Distribution. Poster Session at the CSAIL Industry Affiliates Program (CSAIL-IAP) Annual Meeting, Cambridge, United States of America (the).
HDL: 20.500.12708/85710
Hofbauer, M., Schweiger, K., Gaberl, W., Zimmermann, H., Giesen, U., Langner, F., Schmid, U., Steininger, A. (2013). Single Event Transient Pulse Shape Measurements by On-chip Sense Amplifiers in a Single Inverter for Intermediate Input States under Alpha Particle Irradiation. IEEE Nuclear and Space Radiation Effects Conference (NSREC), San Francisco, United States of America (the).
HDL: 20.500.12708/85741
Hofbauer, M., Schweiger, K., Dietrich, H., Zimmermann, H., Voss, K. O., Merk, B., Schmid, U., Steininger, A. (2012). Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating through a 90 nm Bulk CMOS Inverter Chain. Nuclear and Space Radiation Effects Conference (NSREC), Miami, United States of America (the).
HDL: 20.500.12708/89963
Steininger, A. (2006). The ECS group’s hardware related research activities. Firma Freescale, München, EU.
HDL: 20.500.12708/84590
Steininger, A. (2006). The DARTS project. ESA Workshop, Aarhus, Denmark.
HDL: 20.500.12708/84591
Delvai, M., Steininger, A. (2005). ASPEAR - An Asynchronous 16 Bit RISC Processor Core. Siemens PSE Technology Day, Vienna, Austria, Austria.
HDL: 20.500.12708/84458

Theses

2024

Baumann, D. (2024). Simulating chemical reactions with a well-founded lattice Boltzmann approach [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2024.120609 / Download: PDF
Haschke, O. (2024). Comparison of QDI adders [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2024.107664 / Download: PDF
Müllner, M. (2024). Modeling resource utilization for spiking neural networks in FPGAs [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2024.94824 / Download: PDF
Spitzer, J. (2024). Implementation of an automated fault-injection framework for QDI circuits [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2024.107665 / Download: PDF
Tabassam, Z. (2024). Utilizing and extending the inherent fault tolerance properties of asynchronous QDI circuits [Dissertation, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2024.122341 / Download: PDF

2023

Wiedemann, S. M. (2023). go2async: a high-level synthesis tool for asynchronous circuits based on click-elements [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2023.97424 / Download: PDF

2022

Pircher, C. (2022). Smart SoC testing and remote configuration facilitated by the use of IJTAG complemented with on-chip microprocessor access [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2022.98141 / Download: PDF
Dür, W. (2022). Fault-tolerant GALS architecture based on pausable clocking [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2022.88760 / Download: PDF
Schwendinger, M. (2022). Evaluation of different tools for design and fault-injection of asynchronous circuits [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2022.98624 / Download: PDF

2021

Behal, P. (2021). Quantitative Comparison of the sensitivity of delay-insensitive design templates to transient faults [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2021.81601 / Download: PDF
Telesklav, M. (2021). Implementations, improvements implications of hardware-assisted CFG-based control flow integrity schemes [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2021.72945 / Download: PDF

2019

Ramsl, W. (2019). Fault masking in synchronous and in asynchronous logic - a comparsion [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2019.25573 / Download: PDF

2018

Obermüller, J. (2018). SoC FPGA Oszilloskop : Implementierung eines Oszilloskops auf einem FPGA mit eingebettetem Prozessor [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/80024
Fritz, B. (2018). Operation and verification framework for the FRad experimental ASIC [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2018.23746 / Download: PDF

2017

Schütz, M. (2017). COTS FPGAs in space : From old concerns to new possibilities [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2017.54551 / Download: PDF
Huemer, F. F. (2017). Protecting 4-phase delay-insensitive communication against transient faults [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2017.30269 / Download: PDF
Savulimedu Veeravalli, V. (2017). Design of custom ASIC for radiation experiments to study single event effects [Dissertation, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2017.48221 / Download: PDF

2016

Hermann, C. (2016). ASCARTS - design of an asynchronous processor using a high-level specification language [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2016.21820 / Download: PDF

2014

Lechner, J. (2014). Building robust GALS circuits : fault-tolerant and variation-aware design. Techniques for reliable circuit operation [Dissertation, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2014.25096 / Download: PDF
Resch, S. (2014). Composability for fail-safe safety-critical systems [Dissertation, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2014.27500 / Download: PDF
Trenkwalder, C. (2014). Effekte von Stuck-At Faults in Delay-Insensitiver Logik [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2014.26284 / Download: PDF
Kutschera, R. (2014). Efficient interfacing between timing domains [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2014.25542 / Download: PDF
Maier, J. (2014). Online test vector insertion - a concurrent built-in self-testing (CBIST) approach for asynchronous logic [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2014.25295 / Download: PDF
Heinisch, A. (2014). Selection and hardware-implementation of an efficient consensus algorithm for a mesochronous system [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2014.22245 / Download: PDF

2013

Hagmann, A. (2013). Performance aware hardware runtime monitors [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/159732
Pados, K. D. (2013). Design and evaluation of an AXI4 bus system [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/159734
Naqvi, S. R. (2013). A non-blocking fault-tolerant asynchronous networks-on-chip router [Dissertation, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2013.22599 / Download: PDF
Hechinger, O. (2013). Analysis of the failure behavior of memory management units [Diploma Thesis, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2013.23180 / Download: PDF
Polzer, T. (2013). A digital metastability model for VLSI circuits [Dissertation, Technische Universität Wien]. reposiTUm.
DOI: 10.34726/hss.2013.22620 / Download: PDF

2012

Panhofer, T. (2012). Self-healing asynchronous circuits for high-reliability applications [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-47033
HDL: 20.500.12708/11331 / Download: PDF
Fuchs, B. (2012). Elaboration of a Fault-tolerance strategy for space-borne digital signal processing applications [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-46481
HDL: 20.500.12708/11402 / Download: PDF
Ferringer, M. (2012). Asynchronous logic in real-time systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-46960
HDL: 20.500.12708/11411 / Download: PDF

2011

Birner, M. (2011). SPEAR2C : implementation of a cache controller for SPEAR2 [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-59473
HDL: 20.500.12708/10682 / Download: PDF
Friesenbichler, W. (2011). Effects and mitigation of transient faults in quasi delay-insensitive logic [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-48162
HDL: 20.500.12708/11332 / Download: PDF
Resch, S. (2011). Hardware description with timing requirements [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-48081
HDL: 20.500.12708/10654 / Download: PDF
Najvirt, R. (2011). Description methods for asynchronous circuits : a comparison [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-41766
HDL: 20.500.12708/12697 / Download: PDF
Burker, A. (2011). Implementation of the TTP/A protocol and WCET analysis on the SPEAR2 platform [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/160444
Walter, M. (2011). The SPEAR2 Hardware/Software Interface [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/159954

2010

Hofer, M. (2010). Generic microprocessor-controlled test unit [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/159779

2009

Ambrosch, K. (2009). Mapping stereo matching algorithms to hardware [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-29639
HDL: 20.500.12708/8962
Tummeltshammer, P. (2009). Analysis of common cause faults in dual core architectures [Dissertation, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/186533
Jahn, P. (2009). Automated regression testing of embedded devices [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/186055
Widtmann, C. (2009). High-level system modeling with SystemC and TLM [Master Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-25914
HDL: 20.500.12708/14675 / Download: PDF
Fuchs, G. (2009). Fault-tolerant distributed algorithms for on-chip tick generation: concepts, implementations and evaluations [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-33442
HDL: 20.500.12708/13033 / Download: PDF
Polzer, T. (2009). Fault-tolerant hardware implementation of a consensus algorithm [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-37200
HDL: 20.500.12708/12587 / Download: PDF

2008

Armengaud, E. (2008). A transparent online test approach for time-triggered communication protocols [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-23226
HDL: 20.500.12708/11092 / Download: PDF
Fletzer, M. (2008). SPEAR2 - an improved version of SPEAR [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-19088
HDL: 20.500.12708/11836 / Download: PDF
Mosser, J. (2008). AMBA4SPEAR2: an AMBA extension module for the SPEAR2 processor core [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-27846
HDL: 20.500.12708/11047 / Download: PDF
Klein, W. (2008). Self-oscillation as a time-reference in asynchronous logic - the UART example [Master Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-20396
HDL: 20.500.12708/10909 / Download: PDF
Lechner, J. (2008). Implementation of a design tool for generation of FSL circuits [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/182090
Jeitler, M. (2008). Optimization of FSL gates [Master Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/183557

2007

Prokop, H. (2007). Reconfigurable hardware implementation of polynomial arithmetic over the finite field GF(3) [Master Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/178009

2006

Varga, C. (2006). Analyse der Implementierbarkeit einer aktiven Schallunterdrückungslösung in Hardware [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-32417
HDL: 20.500.12708/12081 / Download: PDF
Krupnik, L. (2006). Oszillatorische Blutdruckmessung für Patienten mit Rotationsblutpumpen [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/186913
Ferringer, M. (2006). An asynchronous hardware design for distributed tick generation [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/179556

2005

Schöberl, M. (2005). JOP: a Java optimized processor for embedded real-time systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-9003
HDL: 20.500.12708/9614 / Download: PDF
Rahbaran, B. (2005). An experimental comparison of robustness between synchronous and asynchronous logic design [Dissertation, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/177677
Kottke, T. (2005). Untersuchung von fehlertoleranten Prozessorarchitekturen für sicherheitsrelevante Automobilanwendungen [Dissertation, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/177711
Gallo, R. (2005). Revision and verification of an enhanced UART [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/180580
Huber, W. (2005). Design of an asynchronous processor based on code alternation logic - exploration of delay insensitivity [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-18234
HDL: 20.500.12708/13907 / Download: PDF

2004

Handl, T. (2004). Implementierung eines FPGA-basierten Hardware-Fehlerinjektors [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/184082
Tummeltshammer, P. (2004). Multiple constant multiplication by time-multiplexed mapping of addition chains [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/184119
Delvai, M. (2004). Design of an asynchronous processor based on code alternation logic - treatment of non-linear data paths [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-13195
HDL: 20.500.12708/9609 / Download: PDF

2003

Fuchs, G. (2003). A superscalar 16 bit microcontroller for real-time applications [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-11271
HDL: 20.500.12708/12155 / Download: PDF
Pedram, T. (2003). Asynchrone Realisierung einer Arithmetic Logic Unit [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/183013
Winkler, M. (2003). Integrating time-triggered distributed system design in MATLAB/Simulink [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/183455
Eggenhofer, M. (2003). Entwicklung eines USB fullspeed VHDL-Cores [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/183637
El Salloum, C. (2003). Realisierung eines generischen Online Debuggers für Embedded Systems [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/185821
Rieder, B. (2003). Xerxes error behavior [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-10803
HDL: 20.500.12708/8680 / Download: PDF

2002

Resanka, C. (2002). Communication protocol test device in VHDL [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/186234
Eisenmann, U. (2002). Design and implementation of a highly efficient communication node for real-time applications [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/185224
Jankela, M. (2002). Realization of a re-usable offline debugger for the SPEAR micro-controller [Diploma Thesis, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/185819

2001

Vilanek, J. (2001). Zur Rolle der Verifikation im Designprozess digitaler integrierter Schaltungen [Dissertation, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/179306
Thaller, K. (2001). A transparent online memory test [Dissertation, Technische Universität Wien]. reposiTUm.
HDL: 20.500.12708/180075

And more…

Soon, this page will include additional information such as reference projects, activities as journal reviewer and editor, memberships in councils and committees, and other research activities.

Until then, please visit Andreas’s research profile in TISS.

Academic Bio

Andreas Steininger is leading a VLSI design team at the Institute. He received his Diplomingenieur degree (MS) in Electrical Engineering in 1988 and the PhD in Computer Engineering in 1994, both from the TU Wien. In 1999 Steininger received his “venia docendi” in Computer Engineering. He held visiting positions at the Siemens Research Center in Munich and at Logic Vision in San Jose, CA.

Steininger has been involved in many industrial and scientific projects concerned with real-time communication networks (X-by-wire, TTA), the design of fault-tolerant / radiation-tolerant computer architectures and their evaluation by means of fault-injection (PDCS, EXTRACT,FATAL, EASET), testing (built-in self-test, on-line testing) (STEACS, CEVTES), asynchronous logic design (DARTS, ENROL). His current research focuses on asynchronous (“clockless”) logic design, timing-domain interfacing, metastability, and GALS architectures. He has published 150+ papers in journals and at international conferences (see TU Wien publication database), and is co-inventor of 10+ patents. Much of his scientific work was done in cooperation with industrial partners like Intel, Bosch, RUAG Space, Thales, Elektrobit, Audi, TTTech, Gleichmann Research, Frequentis, Daimler Chrysler, Elin, Festo etc.

Steininger is a member of the IEEE and served as PC member and steering committee member for many conferences, was PC Chair of ASYNC 2014, MEDIAN Finale Workshop 2015, DDECS 2016, ASYNC 2020, and local host/General Chair of DDECS 2010 and ASYNC 2018. With respect to teaching Steininger is contributing to the (Bachelor and Master) curriculum of Computer Engineering at the Faculty of Informatics, mainly with his courses on Digital Design, Advanced Digital Design and HW/SW Codesign. He has given invited lectures at international universities and summer schools.

He has supervised 20+ successful PhD theses and serves as the Director for the Vienna PhD School of Informatics and as chair of the Doctoral College Resilient Embedded Systems. Three of his master students have been winners of the faculty’s highly competitive “Distinguished Young Alumnus Award” for the best diploma thesis.