Title: From Vectors to CHERI: RISC-V Virtual Prototypes for Verification and System-Level Exploration

Speaker: Daniel Große, Johannes Kepler University Linz

Time and Date: 11am on May 22, 2026

Seminar Room: DE 02 54

Abstract: RISC-V is widely used for research and development of new processor extensions and system architectures. This flexibility is a major strength, but it also creates a need for tools that allow early evaluation, testing, and software bring-up before hardware is available. This talk presents our work on RISC-V virtual prototypes as executable platforms for verification and system-level exploration. I will first give an overview of RISC-V VP++, an extensible virtual platform for running and evaluating RISC-V systems, from bare-metal applications to full Linux-based software stacks. I will then discuss RVVTS, a test framework for RISC-V Vector implementations, with a focus on differential testing and isolation of failing instructions. Recent extensions of this work expand the approach to floating-point behavior in both RISC-V simulators and RTL designs, covering corner cases such as NaN handling, exception flags, and architectural state differences. Finally, the talk will move from ISA-level verification to system-level security exploration with our integration of CHERI capabilities into a RISC-V virtual prototype. CHERI introduces hardware-supported capabilities for fine-grained memory protection and software compartmentalization. The resulting platform enables early investigation of capability-enhanced hardware/software systems, including software bring-up and architectural evaluation, long before mature hardware platforms are available. Overall, the talk shows how virtual prototypes can support the development of RISC-V systems across multiple levels, from ISA-level testing and software execution to architectural exploration and system-level evaluation.

BIO: Daniel Große is a full professor at Johannes Kepler University Linz, Austria, where he heads the Institute for Complex Systems (ICS) and the LIT Secure and Correct Systems Lab. His research focuses on verification, virtual prototyping, debugging, synthesis, and RISC-V-based system design, with an emphasis on methods and tools for building reliable hardware/software systems. He received his Diploma in Computer Science from the University of Freiburg and his Dr.-Ing. degree in Computer Science from the University of Bremen. Before joining JKU in 2020, he held academic and research positions at the University of Bremen, the University of Freiburg, and the German Research Center for Artificial Intelligence. He was also CEO of the EDA start-up solvertec, which focused on automated debugging techniques, and Scientific Coordinator of the Graduate School System Design funded within the German Excellence Initiative. He has published more than 190 peer-reviewed papers, served on the program committees of major conferences such as DAC, DATE, ICCAD, ASP-DAC, CODES+ISSS, GLSVLSI, FDL, and MEMOCODE, and received several best paper and innovation awards. He is an IEEE Senior Member and an Allied Member of the Accellera Systems Initiative in the SystemC Verification Working Group.