Summer 2026

• Introduction to Logical Methods in Computer Science / 184.766 VO
• Research Seminar LogiCS / 184.767 SE

Winter 2025

• Advanced Computer Architecture / 191.019 VU
• Advanced Digital Design / 182.755 VU
• Advanced Multiprocessor Programming / 191.022 VU
• Advanced Topics in Verification and Synthesis for AI-Enabled Cyber-Physical Systems / 199.030 VU
• Bachelor Thesis for Computer Science and Business Informatics / 182.698 PR
• Computer Engineering Practical / 191.005 PR
• Computer Engineering Project / 191.006 PR
• Computer Networks / 182.752 VU
• Current Trends in Computer Science / 195.072 VU
• Digital Design / 182.693 VO
• Doctorand's seminar / 182.070 SE
• From surviving to thriving: crafting your good professional life / 199.096 VU
• Hardware Modeling / 191.011 VU
• HW/SW Codesign / 182.701 LU
• HW/SW Codesign / 182.700 VU
• Knowledge Representation for Robotics, Automotive, and SmartCities / 199.031 VU
• Orientation Bachelor with Honors of Informatics and Business Informatics / 180.767 SE
• Philosophy of Science / 195.080 VU
• Project in Computer Science 1 / 191.008 PR
• Project in Computer Science 2 / 191.009 PR
• Propädeutikum für Informatik / 180.771 VU
• Research Seminar LogiCS / 184.767 SE
• Scientific Project Computer Engineering / 191.007 PR
• Scientific Research and Writing / 193.052 SE
• Seminar Computer Engineering / 182.757 SE
• Seminar for Master Students in Computer Engineering / 180.778 SE
• SMT Solving Internals / 199.029 VU
• Weighted Automata and Weighted Logics / 199.032 VU

2025

• DOMINO: ML DevOps Methods for a Green and Safe EdgeAI Lifecycle
  2025 – 2028 / Austrian Research Promotion Agency (FFG)
• GenerIoT - Unterauftrag: Generating and Deploying Lightweight, Secure and Zero-overhead Software for Multipurpose IoT Devices
  2025 – 2026 / XCoorp GmbH
• TÜV-trustworthy electronics
  2025 – 2026 / TÜV Austria Holding AG

2023

• TA-CPS: Trustworthy Autonomous Cyber-Physical Systems
  2023 – 2028 / TTTech Auto AG / Publications (3)

2020

• ByzDEL: Reasoning about Knowledge in Byzantine Distributed Systems
  2020 – 2025 / Austrian Science Fund (FWF) / Website / Publications (37)

2019

• Intel CARS 2: Robust Atomic Computing Platform and Enhanced Fault-Tolerant Distributed Algorithms 2
  2019 – 2028 / Intel Corporation
• DMAC: Digital Modeling of Asynchronous Integrated Circuits
  2019 – 2024 / Austrian Science Fund (FWF) / Publications (16)

2017

• IoT4CPS: Trustworthy IoT for CPS
  2017 – 2020 / Austrian Research Promotion Agency (FFG) / Publication
• Intel CARS: Robust Atomic Computing Platform and Enhanced Fault-Tolerant Distributed Algorithms
  2017 – 2019 / Intel Corporation / Publications (3)

2016

• ADynNet: Gracefully Degrading Agreement in Directed Dynamic Networks
  2016 – 2020 / Austrian Science Fund (FWF) / Publications (2)

2014

• EASET: Analysis & Modeling of Single-Event-Transients in VLSI Chips
  2014 – 2017 / Austrian Science Fund (FWF) / Publications (4)

2013

• SIC: Self-stabilizing Byzantine Fault-Tolerant Distributed Algorithms for Integrated Circiuts
  2013 – 2018 / Austrian Science Fund (FWF) / Publication
• CDPP: Configurable Data Prcessing Platform
  2013 – 2014 / Austrian Research Promotion Agency (FFG)

2012

• MMU: Fehleranalyse MMU
  2012 / Robert Bosch GmbH

2011

• Rise-TOOLS: Tools for Concurrent and distributed Systems
  2011 – 2019 / Austrian Science Fund (FWF) / Publication
• PROSEED: Proof Seeding for Software Verification
  2011 – 2015 / Vienna Science and Technology Fund (WWTF) / Publications (2)

2010

• CEVTES: CounterExample Validation and Test Case Generation Framework for Verifiying Embedded Software
  2010 – 2013 / Austrian Research Promotion Agency (FFG) / Publications (10)

2008

• PSRTS: Partially Synchronous Distributed Real-Time Systems
  2008 – 2012 / Austrian Science Fund (FWF)
• FAME: Fault Models for Engineering
  2008 – 2010 / Austrian Research Promotion Agency (FFG)

2007

• ARTS: Asynchronous Logic in Real-Time Systems
  2007 – 2011 / Austrian Research Promotion Agency (FFG) / Publications (6)

2006

• TRAFT: Transient Fault Tolerance
  2006 – 2010 / Austrian Research Promotion Agency (FFG)

2005

• DARTS: Distributed Algorithms for Robust Tick Synchronization
  2005 – 2010 / Austrian Research Promotion Agency (FFG) / Website / Publications (18)
• SPAWN: Fault-tolerant Distributed Algorithms in Sparse Ad Hoc Wireless Networks
  2005 – 2009 / Austrian Science Fund (FWF) / Website
• EXTRACT: Exploiting Synchrony for Transparent Communication Services Testing
  2005 – 2008 / Austrian Research Promotion Agency (FFG) / Website / Publications (10)

2004

• ASSERT: Automated proof based System and Software Engineering for Real-Time Applications
  2004 – 2008 / European Commission / Website
• THETA: Asynchronous Distributed Algorithms in the Theta-Model
  2004 – 2008 / Austrian Science Fund (FWF) / Publication
• DCBA: Distributed Computing in the Presence of Bounded Asynchrony
  2004 – 2007 / Austrian Research Promotion Agency (FFG)
• SCDL: Seamless Campus - Distance Labs
  2004 – 2007 / Austrian Research Promotion Agency (FFG) / Publications (2)

2003

• STEACS: Systematic Test of Embedded Automotive Communication Systems
  2003 – 2008 / Austrian Research Promotion Agency (FFG) / Publications (19)

2025

• Thoma, M., Aghajanzadeh, E., Balamuthu Sampath, S., Mori, P., Fasfous, N., Frickenstein, A., Vemparala, M.-R., Mueller-Gritschneder, D., Schlichtmann, U. (2025). SuperFast: Fast Supernet Training Using Initial Knowledge. In 2025 62nd ACM/IEEE Design Automation Conference (DAC) (pp. 1–7). IEEE. Peer-reviewed.
  DOI: 10.1109/DAC63849.2025.11132779
• Klotz, S., Kulkarni, S., Joglekar, N., Bucksch, T., Goswami, D., Mueller-Gritschneder, D. (2025). Sim-to-Real: Tiny Deep Learning Agents on Resource-Constrained Embedded Microcontrollers. In 2025 IEEE Conference on Control Technology and Applications (CCTA) (pp. 806–811). IEEE. Peer-reviewed.
  DOI: 10.1109/CCTA53793.2025.11151414
• Lehninger, P., Jantsch, A., Steininger, A., Worsey, E., Marot, V., Pamunuwa, D. (2025). Muller C-Element for NEMS. In 2025 29th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) (pp. 56–62). IEEE. Peer-reviewed.
  DOI: 10.34726/10060 / Download: PDF
• Geier, J., Kontopoulos, L., Müller-Gritschneder, D., Schlichtmann, U. (2025). Rapid Fault Injection Simulation by Hash-Based Differential Fault Effect Equivalence Checks. In 2025 Design, Automation Test in Europe Conference (DATE). 2025 Design, Automation Test in Europe Conference (DATE), Lyon, France. IEEE. Peer-reviewed.
  DOI: 10.23919/DATE64628.2025.10993266
• Ferdowsi, A., Függer, M., Nowak, T., Schmid, U., Drmota, M. (2025). Faithful dynamic timing analysis of digital circuits using continuous thresholded mode-switched ODEs. NONLINEAR ANALYSIS-HYBRID SYSTEMS, 56, Article 101572. Peer-reviewed.
  DOI: 10.1016/j.nahs.2024.101572 / Download: PDF / Project: DMAC
• Felber, S., Galeana, H. R. (2025). Stabilizing Consensus Is Impossible in Lossy Iterated Immediate Snapshot Models. In S. Bonomi, L. Galletta, E. Rivière, V. Schiavoni (Eds.), 28th International Conference on Principles of Distributed Systems (OPODIS 2024) (pp. 18:1-18:16). Peer-reviewed.
  DOI: 10.4230/LIPIcs.OPODIS.2024.18
• Körber, N., Kromer, E., Siebert, A., Hauke, S., Mueller-Gritschneder, D., Schuller, B. (2025). EGIC: Enhanced Low-Bit-Rate Generative Image Compression Guided by Semantic Segmentation. In A. Leonardis, E. Ricci, S. Roth (Eds.), Computer Vision – ECCV 2024 : 18th European Conference, Milan, Italy, September 29 – October 4, 2024, Proceedings, Part XXXV (pp. 202–220). Springer. Peer-reviewed.
  DOI: 10.1007/978-3-031-72761-0_12

2024

• Nowak, T., Schmid, U., Winkler, K. (2024). Topological Characterization of Consensus in Distributed Systems. Journal of the ACM, 71(6), 1–48. Peer-reviewed.
  DOI: 10.1145/3687302 / Projects: DMAC, ByzDEL
• Foik, C., Kunzelmann, R., Mueller-Gritschneder, D., Schlichtmann, U. (2024). Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 43(11), 4130–4141. Peer-reviewed.
  DOI: 10.1109/TCAD.2024.3445255
• van Kempen, P., Salmen, M., Müller-Gritschneder, D., Schlichtmann, U. (2024). Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization. In Proceedings 2024 27th Euromicro Conference on Digital System Design (DSD 2024) (pp. 335–342). Peer-reviewed.
  DOI: 10.1109/DSD64264.2024.00052
• Fiedler, C., Huemer, F., Steininger, A. (2024). Synchronizing Independent Ring Oscillators on an FPGA. In 2024 Austrochip Workshop on Microelectronics (Austrochip) (pp. 1–4). Peer-reviewed.
  DOI: 10.1109/Austrochip62761.2024.10716225
• Cignarale, G., Kuznets, R. (2024). A priori Belief Updates as a Method for Agent Self-recovery. Review of Analytic Philosophy, 4(1).
  DOI: 10.18494/SAM.RAP.2024.0021 / Project:
• Wiedemann, S. M., Zwirchmayr, J., Steininger, A. (2024). Towards Software-Based Vendor-Independent Preemption for Hardware Accelerated Workloads. In 2024 Austrochip Workshop on Microelectronics (Austrochip). 2024 Austrochip Workshop on Microelectronics, Wien, Austria.
  DOI: 10.1109/Austrochip62761.2024.10716010
• Hoffman, A., Fnayou, A., Smirnov, F., Müller-Gritschneder, D., Schlichtmann, U. (2024). MuDSE: GA-ILP-based Framework for Automated Deployment of Multiple DNNs on Heterogeneous Mixed-Criticality Systems. In 2024 IEEE International Conference on Omni-layer Intelligent Systems (COINS). IEEE COINS 2024: IEEE International Conference on Omni-layer Intelligent systems, London, United Kingdom of Great Britain and Northern Ireland (the). IEEE. Peer-reviewed.
  DOI: 10.1109/COINS61597.2024.10622135
• Ditmarsch, H. van, Fruzsa, K., Kuznets, R., Schmid, U. (2024). A Logic for Repair and State Recovery in Byzantine Fault-Tolerant Multi-agent Systems. In Automated Reasoning: 12th International Joint Conference, IJCAR 2024, Nancy, France, July 3-6, 2024, Proceedings, Part II (pp. 114–134). Springer.
  DOI: 10.1007/978-3-031-63501-4_7 / Projects: DMAC, ByzDEL
• Huang, Y., Wang, H., Qiao, X., Su, X., Li, Y., Dustdar, S., Zhang, P. (2024). SCAXR: Empowering Scalable Multi-User Interaction for Heterogeneous XR Devices. IEEE Network, 38(4), 250–258. Peer-reviewed.
  DOI: 10.1109/MNET.2023.3320440
• Winkler, K., Paz, A., Rincon Galeana, H., Schmid, S., Schmid, U. (2024). The Time Complexity of Consensus Under Oblivious Message Adversaries. Algorithmica, 86(6), 1830–1861. Peer-reviewed.
  DOI: 10.1007/s00453-024-01209-4
• Rincon Galeana, H., Schmid, U. (2024). Network Abstractions for Characterizing Communication Requirements in Asynchronous Distributed Systems. In Structural Information and Communication Complexity : 31st International Colloquium, SIROCCO 2024, Vietri sul Mare, Italy, May 27–29, 2024, Proceedings (pp. 501–506). Springer.
  DOI: 10.1007/978-3-031-60603-8_29 / Projects: DMAC, ByzDEL
• Huemer, F. (2024). QDI Binary Comparator Networks and their Application in Combinational Logic. In 2024 27th International Symposium on Design Diagnostics of Electronic Circuits Systems (DDECS) (pp. 92–97). Peer-reviewed.
  DOI: 10.1109/DDECS60919.2024.10508908
• Cignarale, G., Kuznets, R., Schlögl, T. (2024). Minimizing Agents’ State Corruption Resulting from Leak-Free Epistemic Communication Modeling. In Foundations of Information and Knowledge Systems (pp. 165–181). Springer. Peer-reviewed.
  DOI: 10.1007/978-3-031-56940-1_9 / Projects: DMAC, ByzDEL
• Ferdowsi, A., Függer, M., Salzmann, J., Schmid, U. (2024). A Hybrid Delay Model for Interconnected Multi-Input Gates. In 2023 26th Euromicro Conference on Digital System Design (DSD) (pp. 381–390). IEEE.
  DOI: 10.1109/DSD60849.2023.00060 / Project: DMAC
• Castañeda, A., Ditmarsch, H. van, Kuznets, R., Moses, Y., Schmid, U. (2024). Epistemic and Topological Reasoning in Distributed Systems. Dagstuhl Reports, 13(7), 34–65.
  DOI: 10.4230/DagRep.13.7.34
• Yang, Y., Wu, J., Chen, T., Peng, C., Wang, J., Deng, J., Tao, X., Liu, G., Li, W., Yang, L., He, Y., Yang, T., Aghvami, A. H., Eliassen, F., Dustdar, S., Niyato, D., Sun, W., Xu, Y., Yuan, Y., … Dai, C. (2024). Task-Oriented 6G Native-AI Network Architecture. IEEE Network, 38(1), 219–227. Peer-reviewed.
  DOI: 10.1109/MNET.2023.3321464
• Colucci, A., Steininger, A., Shafique, M. (2024). EISFINN: On the Role of Efficient Importance Sampling in Fault Injection Campaigns for Neural Network Robustness Analysis. In 2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS). 2024 IEEE 30th International Symposium on On-line Testing and Robust System Design (IOLTS), Rennes, Brittany, France. IEEE. Peer-reviewed.
  DOI: 10.1109/IOLTS60994.2024.10616075
• Colucci, A., Steininger, A., Shafique, M. (2024). SBanTEM: A Novel Methodology for Sparse Band Tensors as Soft-Error Mitigation in Sparse Convolutional Neural Networks. In 2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS). 2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS), Rennes, Brittany, France. IEEE. Peer-reviewed.
  DOI: 10.1109/IOLTS60994.2024.10616070
• Scharwitzl, C., Steininger, A. (2024). An Autonomous Clock Frequency Supervision Circuit. In 2024 27th International Symposium on Design Diagnostics of Electronic Circuits Systems (DDECS) (pp. 25–30). Peer-reviewed.
  DOI: 10.1109/DDECS60919.2024.10508917
• Wiedemann, S., Zwirchmayr, J., Steininger, A. (2024). Towards Software-Based Vendor-Independent Preemption for Hardware Accelerated Workloads. In 2024 Austrochip Workshop on Microelectronics (Austrochip). 2024 Austrochip Workshop on Microelectronics (Austrochip), Vienna, Austria. IEEE. Peer-reviewed.
  DOI: 10.1109/Austrochip62761.2024.10716010
• Steininger, A. (2024). Asynchronous Circuits – Old Iron or Enabler for a New Resilience Level of Digital Circuits? In H. Kubátová, P. Fišer, J. Borecký (Eds.), Proceedings of the 12th Prague Embedded Systems Workshop (pp. 2–2). Czech Technical University.
  HDL: 20.500.12708/208721

2023

• Ostrowski, E., Shafique, M. (2023). ISLE: A Framework for Image Level Semantic Segmentation Ensemble. In G. Bebis, G. Ghiasi, Y. Fang, A. Sharf, Y. Dong, C. Weaver, Z. Leo, J. J. LaViola Jr., L. Kohli (Eds.), Advances in Visual Computing : 18th International Symposium, ISVC 2023, Lake Tahoe, NV, USA, October 16–18, 2023. Proceedings, Part I (pp. 41–52). Springer. Peer-reviewed.
  DOI: 10.1007/978-3-031-47966-3_4
• Prabakaran, B. S., Ostrowski, E., Shafique, M. (2023). ReFit: A Framework for Refinement of Weakly Supervised Semantic Segmentation Using Object Border Fitting for Medical Images. In G. Bebis, G. Ghiasi, Y. Fang, A. Sharf, Y. Dong, C. Weaver, Z. Leo, J. J. LaViola, L. Kohli (Eds.), Advances in Visual Computing : 18th International Symposium, ISVC 2023, Lake Tahoe, NV, USA, October 16–18, 2023. Proceedings, Part I (pp. 44–55). Springer. Peer-reviewed.
  DOI: 10.1007/978-3-031-47969-4_4
• Prabakaran, B. S., Mrazek, V., Vasicek, Z., Sekanina, L., Shafique, M. (2023). Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD). 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Francisco, United States of America (the). IEEE.
  DOI: 10.1109/ICCAD57390.2023.10323678
• Girlando, M., Kuznets, R., Marin, S., Morales, M., Straßburger, L. (2023). A decision procedure for IS4. In Workshop on Proof Theory, Modal Logic and Reflection Principles, Wormshop 2023, Bern, Booklet of abstracts. Wormshop 2023: Workshop on Proof Theory, Modal Logic and Reflection Principles, Bern, Switzerland. Invited.
  DOI: 10.34726/5415 / Download: PDF / Project: ByzDEL
• Kuznets, R. (2023). Simplicial approaches to crashing agents. In Workshop on Proof Theory, Modal Logic and Reflection Principles, Wormshop 2023, Bern, Booklet of abstracts. Wormshop 2023: Workshop on Proof Theory, Modal Logic and Reflection Principles, Bern, Switzerland. Invited and peer-reviewed.
  DOI: 10.34726/5476 / Download: PDF / Project: ByzDEL
• Randrianomentsoa, R. F., van Ditmarsch, H., Kuznets, R. (2023). Impure simplicial complexes: complete axiomatization. Logical Methods in Computer Science, 19(4), Article 3. Peer-reviewed.
  DOI: 10.46298/lmcs-19(4:3)2023 / Download: PDF / Project: ByzDEL
• Putra, R. V. W., Shafique, M. (2023). A Design Methodology for Energy-Efficient Embedded Spiking Neural Networks. In S. Pasricha M. Shafique (Eds.), Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing : Use Cases and Emerging Challenges (pp. 15–35). Springer.
  DOI: 10.1007/978-3-031-39932-9_2
• Marchisio, A., Shafique, M. (2023). Embedded Neuromorphic Using Intel’s Loihi Processor. In S. Pasricha M. Shafique (Eds.), Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing : Use Cases and Emerging Challenges (pp. 137–172). Springer.
  DOI: 10.1007/978-3-031-39932-9_6
• Prabakaran, B. S., Shafique, M. (2023). An End-to-End Embedded Neural Architecture Search and Model Compression Framework for Healthcare Applications and Use-Cases. In S. Pasricha M. Shafique (Eds.), Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing : Use Cases and Emerging Challenges (pp. 21–43). Springer.
  DOI: 10.1007/978-3-031-40677-5_2
• Marchisio, A., Hanif, M. A., Shafique, M. (2023). Adversarial ML for DNNs, CapsNets, and SNNs at the Edge. In S. Pasricha M. Shafique (Eds.), Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing : Use Cases and Emerging Challenges (pp. 463–496). Springer.
  DOI: 10.1007/978-3-031-40677-5_18
• Naseer, M., Bhatti, I. T., Hasan, O., Shafique, M. (2023). Considering the Impact of Noise on Machine Learning Accuracy. In S. Pasricha M. Shafique (Eds.), Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing : Use Cases and Emerging Challenges (pp. 377–394). Springer.
  DOI: 10.1007/978-3-031-40677-5_15
• Putra, R. V. W., Hanif, M. A., Shafique, M. (2023). An Off-Chip Memory Access Optimization for Embedded Deep Learning Systems. In S. Pasricha M. Shafique (Eds.), Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing : Hardware Architectures (pp. 175–198). Springer.
  DOI: 10.1007/978-3-031-19568-6_6
• Putra, R. V. W., Hanif, M. A., Shafique, M. (2023). Massively Parallel Neural Processing Array (MPNA): A CNN Accelerator for Embedded Systems. In S. Pasricha M. Shafique (Eds.), Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing : Use Cases and Emerging Challenges (pp. 3–24). Springer.
  DOI: 10.1007/978-3-031-19568-6_1
• Naseer, M., Hasan, O., Shafique, M. (2023). QuanDA: GPU accelerated quantitative deep neural network analysis. ACM Transactions on Design Automation of Electronic Systems, 28(6), 1–21. Peer-reviewed.
  DOI: 10.1145/3611671 / Download: PDF
• van Ditmarsch, H., Kuznets, R., Randrianomentsoa, R. (2023). On Two- and Three-valued Semantics for Impure Simplicial Complexes. In A. Achilleos D. Della Monica (Eds.), Proceedings of the Fourteenth International Symposium on Games, Automata, Logics, and Formal Verification (pp. 50–66). Open Publishing Association.
  DOI: 10.4204/EPTCS.390.4 / Download: PDF / Project: ByzDEL
• Ahmadi, M. M., Alrahis, L., Sinanoglu, O., Shafique, M. (2023). FPGA-Patch: Mitigating Remote Side-Channel Attacks on FPGAs using Dynamic Patch Generation. In 2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED). 2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Wien, Austria. IEEE.
  DOI: 10.1109/ISLPED58423.2023.10244526
• van der Giessen, I., Jalali, R., Kuznets, R. (2023). Extensions of K5: Proof Theory and Uniform Lyndon Interpolation. In D. R. S. Ramanayake J. Urban (Eds.), Automated Reasoning with Analytic Tableaux and Related Methods: 32nd International Conference, TABLEAUX 2023, Prague, Czech Republic, September 18–21, 2023, Proceedings (pp. 263–282). Springer.
  DOI: 10.1007/978-3-031-43513-3_15 / Download: PDF / Project: ByzDEL
• Cignarale, G., Kuznets, R., Rincón Galeana, H., Schmid, U. (2023). Logic of Communication Interpretation: How to Not Get Lost in Translation. In U. Sattler M. Suda (Eds.), Frontiers of Combining Systems: 14th International Symposium, FroCoS 2023, Prague, Czech Republic, September 20–22, 2023. Proceedings (pp. 119–136). Springer.
  DOI: 10.1007/978-3-031-43369-6_7 / Download: PDF / Project: ByzDEL
• Kuznets, R. (2023). Always Look on Both Sides of Proof: Syntax and Semantics as the Yin and Yang of Structural Proof Theory. In D. R. S. Ramanayake J. Urban (Eds.), Automated Reasoning with Analytic Tableaux and Related Methods: 32nd International Conference, TABLEAUX 2023, Prague, Czech Republic, September 18–21, 2023, Proceedings. Springer. Invited and peer-reviewed.
  DOI: 10.34726/5327 / Download: PDF / Project: ByzDEL
• Tabassam, Z., Steininger, A., Najvirt, R., Huemer, F. (2023). ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. In 2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) (pp. 48–57). IEEE. Peer-reviewed.
  DOI: 10.1109/ASYNC58294.2023.10239589
• Shehaby, R. E., Függer, M., Steininger, A. (2023). On the Susceptibility of QDI Circuits to Transient Faults. In L. Petrucci J. Sproston (Eds.), Formal Modeling and Analysis of Timed Systems : 21st International Conference, FORMATS 2023, Antwerp, Belgium, September 19–21, 2023, Proceedings (pp. 69–85). Springer LNCS. Peer-reviewed.
  DOI: 10.1007/978-3-031-42626-1_5
• Colucci, A. (2023). Towards Transient Fault Mitigation Techniques Optimized for Compressed Neural Networks. In 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S) (pp. 211–213). IEEE. Peer-reviewed.
  DOI: 10.1109/DSN-S58398.2023.00059
• Tabassam, Z., Steininger, A. (2023). SET Effects on Quasi Delay Insensitive and Synchronous Circuits. In 2023 IEEE European Test Symposium (ETS). Proceedings (pp. 1–6). IEEE. Peer-reviewed.
  DOI: 10.34726/5435 / Download: PDF
• Schlögl, T., Schmid, U. (2023). A Sufficient Condition for Gaining Belief in Byzantine Fault-Tolerant Distributed Systems. In R. Verbrugge (Ed.), Proceedings Nineteenth conference on Theoretical Aspects of Rationality and Knowledge (pp. 487–506). Peer-reviewed.
  DOI: 10.4204/EPTCS.379.37 / Project: DMAC
• Prabakaran, B. S., Hamelmann, P., Ostrowski, E., Shafique, M. (2023). FPUS23: An ultrasound fetus phantom dataset with deep neural network evaluations for fetus orientations, fetal planes, and anatomical features. IEEE Access, 11, 58308–58317. Peer-reviewed.
  DOI: 10.1109/ACCESS.2023.3284315 / Download: PDF
• Cignarale, G., Schmid, U., Tahko, T. E., Kuznets, R. (2023). The Role of A Priori Belief in the Design and Analysis of Fault-Tolerant Distributed Systems. Minds and Machines, 33(2), 293–319. Peer-reviewed.
  DOI: 10.1007/s11023-023-09631-3 / Download: PDF / Project: ByzDEL
• Wicaksana Putra, R. V., Shafique, M. (2023). Mantis: Enabling Energy-Efficient Autonomous Mobile Agents with Spiking Neural Networks. In 2023 9th International Conference on Automation, Robotics and Applications (ICARA) (pp. 197–201). IEEE. Peer-reviewed.
  DOI: 10.1109/ICARA56516.2023.10125781
• Ferdowsi, A., Függer, M., Nowak, T., Schmid, U. (2023). Continuity of Thresholded Mode-Switched ODEs and Digital Circuit Delay Models. In HSCC ’23: Proceedings of the 26th ACM International Conference on Hybrid Systems: Computation and Control. 26th ACM International Conference on Hybrid Systems: Computation and Control (HSCC’23), San Antonio, United States of America (the). Association for Computing Machinery. Peer-reviewed.
  DOI: 10.1145/3575870.3587125 / Project: DMAC
• Putra, R. V. W., Hanif, M. A., Shafique, M. (2023). RescueSNN: enabling reliable executions on spiking neural network accelerators under permanent faults. Frontiers in Neuroscience, 17, Article 1159440. Peer-reviewed.
  DOI: 10.3389/fnins.2023.1159440 / Download: PDF
• Marchisio, A., Nanfa, G., Khalid, F., Hanif, M. A., Martina, M., Shafique, M. (2023). SeVuc: A study on the Security Vulnerabilities of Capsule Networks against adversarial attacks. Microprocessors and Microsystems, 96, Article 104738. Peer-reviewed.
  DOI: 10.1016/j.micpro.2022.104738
• Winkler, K., Paz, A., Galeana, H. R., Schmid, S., Schmid, U. (2023). The Time Complexity of Consensus Under Oblivious Message Adversaries. In Y. T. Kalai (Ed.), 14th Innovations in Theoretical Computer Science Conference (ITCS’23) (pp. 1–28). Schloss-Dagstuhl - Leibniz Zentrum für Informatik.
  DOI: 10.4230/LIPIcs.ITCS.2023.100 / Projects: ByzDEL, ADynNet
• Girlando, M., Kuznets, R., Marin, S., Morales, M., Straßburger, L. (2023). Intuitionistic S4 is decidable. In 2023 38th Annual ACM/IEEE Symposium on Logic in Computer Science (LICS). LICS 2023: Thirty-Eighth Annual ACM/IEEE Symposium on Logic in Computer Science, Boston, MA, United States of America (the). IEEE.
  DOI: 10.34726/5295 / Download: PDF / Project: ByzDEL
• Öhlinger, D., Schmid, U. (2023). A Digital Delay Model Supporting Large Adversarial Delay Variations. In 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (pp. 111–117). Peer-reviewed.
  DOI: 10.1109/DDECS57882.2023.10139680 / Project: DMAC
• Marchisio, A., Teodonio, F., Rizzi, A., Shafique, M. (2023). ISMatch: A real-time hardware accelerator for inexact string matching of DNA sequences on FPGA. Microprocessors and Microsystems, 97, Article 104763. Peer-reviewed.
  DOI: 10.1016/j.micpro.2023.104763
• Ferdowsi, A., Schmid, U., Salzmann, J. (2023). Accurate Hybrid Delay Models for Dynamic Timing Analysis. In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD) (pp. 1–9). IEEE.
  DOI: 10.1109/ICCAD57390.2023.10323646 / Project: DMAC
• Naseer, M., Prabakaran, B. S., Hasan, O., Shafique, M. (2023). UnbiasedNets: a dataset diversification framework for robustness bias alleviation in neural networks. Machine Learning. Peer-reviewed.
  DOI: 10.1007/s10994-023-06314-z / Download: PDF
• Marchisio, A., Dura, D., Capra, M., Martina, M., Masera, G., Shafique, M. (2023). SwiftTron: An Efficient Hardware Accelerator for Quantized Transformers. In 2023 International Joint Conference on Neural Networks (IJCNN). 2023 International Joint Conference on Neural Networks (IJCNN), Gold Coast, Australia. IEEE.
  DOI: 10.1109/IJCNN54540.2023.10191521
• Marchisio, A., De Marco, A., Colucci, A., Martina, M., Shafique, M. (2023). RobCaps: Evaluating the Robustness of Capsule Networks against Affine Transformations and Adversarial Attacks. In 2023 International Joint Conference on Neural Networks (IJCNN). 2023 International Joint Conference on Neural Networks (IJCNN), Gold Coast, Australia. IEEE.
  DOI: 10.1109/IJCNN54540.2023.10190994
• Ostrowski, E., Prabakaran, B. S., Shafique, M. (2023). SILOP: An Automated Framework for Semantic Segmentation Using Image Labels Based on Object Perimeters. In 2023 International Joint Conference on Neural Networks (IJCNN) (pp. 1–9). IEEE. Peer-reviewed.
  DOI: 10.1109/IJCNN54540.2023.10191935
• Ahmadi, M. M., Alrahis, L., Sinanoglu, O., Shafique, M. (2023). ShapeShifter: Protecting FPGAs from Side-Channel Attacks with Isofunctional Heterogeneous Modules. In 2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS). 2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), Kreta, Greece. IEEE.
  DOI: 10.1109/IOLTS59296.2023.10224883
• Putra, R. V. W., Shafique, M. (2023). TopSpark: A Timestep Optimization Methodology for Energy-Efficient Spiking Neural Networks on Autonomous Mobile Agents. In 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS) (pp. 3561–3567).
  DOI: 10.1109/IROS55552.2023.10342499
• Naseer, M., Hasan, O., Shafique, M. (2023). Scaling Model Checking for Neural Network Analysis via State-Space Reduction and Input Segmentation. In N. Narodytska, G. Amir, G. Katz, O. Isac (Eds.), Proceedings of the 6th Workshop on Formal Methods for ML-Enabled Autonomous Systems (pp. 6–28).
  DOI: 10.29007/7r6j
• Naseer, M., Shafique, M. (2023). Poster: Link between Bias, Node Sensitivity and Long-Tail Distribution in trained DNNs. In 2023 IEEE 16th International Conference on Software Testing, Verification and Validation (pp. 474–477). Peer-reviewed.
  DOI: 10.1109/ICST57152.2023.00054
• Girlando, M., Kuznets, R., Marin, S., Morales, M., Straßburger, L. (2023). Decidability of intuitionistic S4. In Logica 2023. Abstracts (pp. 32–33). Peer-reviewed.
  DOI: 10.34726/5418 / Download: PDF / Project: ByzDEL

2022

• Prabakaran, B. S., Fasching, F., Schreib, J., Steininger, A., Shafique, M. (2022). ATLAS: An IoT Architecture and Secure Open-source Networking Stack for Anonymous Localization and Tracking Using Smartphones and Bluetooth Beacons. arXiv.
  DOI: 10.34726/3642 / Download: PDF
• Viale, A., Marchisio, A., Martina, M., Masera, G., Shafique, M. (2022). LaneSNNs: Spiking Neural Networks for Lane Detection on the Loihi Neuromorphic Processor. In Proceedings 2022 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS) (pp. 79–86).
  DOI: 10.1109/IROS47612.2022.9981034
• Ferdowsi, A., Schmid, U., Salzmann, J. (2022). An Accurate Hybrid Delay Model for Multi-Input Gates. arXiv.
  DOI: 10.34726/2942 / Download: PDF / Project: DMAC
• Tabassam, Z., Steininger, A. (2022). SET Hardened Derivatives of QDI Buffer Template. In 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Austin, TX, United States of America (the). IEEE. Peer-reviewed.
  DOI: 10.34726/3944 / Download: PDF
• Elshehaby, R., Steininger, A. (2022). Study and Comparison of QDI Pipeline Components’ Sensitivity to Permanent Faults. In 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Austin, TX, United States of America (the). IEEE. Peer-reviewed.
  DOI: 10.34726/4047 / Download: PDF
• Marchisio, A., Mrazek, V., Massa, A., Bussolino, B., Martina, M., Shafique, M. (2022). RoHNAS: A Neural Architecture Search Framework With Conjoint Optimization for Adversarial Robustness and Hardware Efficiency of Convolutional and Capsule Networks. IEEE Access, 10, 109043–109055. Peer-reviewed.
  DOI: 10.1109/ACCESS.2022.3214312
• Tabassam, Z., Steininger, A. (2022). Towards Resilient QDI Pipeline Implementations. In 2022 25th Euromicro Conference on Digital System Design (DSD) (pp. 657–664). IEEE. Peer-reviewed.
  DOI: 10.34726/3942 / Download: PDF
• Tauner, S. (2022). RIPEMB: A framework for assessing hardware-assisted software security schemes in embedded systems. In ARES ’22: Proceedings of the 17th International Conference on Availability, Reliability and Security (pp. 1–6). Association for Computing Machinery (ACM). Peer-reviewed.
  DOI: 10.1145/3538969.3539013 / Download: PDF
• Tabassam, Z., Naqvi, S. R., Steininger, A. (2022). AμFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages. In 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (pp. 32–37). IEEE. Peer-reviewed.
  DOI: 10.34726/3941 / Download: PDF
• Ferdowsi, A., Dehghan Chenary, M., Khanteymoori, A. (2022). TSCDA: a dynamic two-stage community discovery approach. Social Network Analysis and Mining, 12, Article 46. Peer-reviewed.
  DOI: 10.1007/s13278-022-00874-z
• Stoilkovska, I., Konnov, I., Widder, J., Zuleger, F. (2022). Verifying safety of synchronous fault-tolerant algorithms by bounded model checking. International Journal on Software Tools for Technology Transfer, 24(1), 33–48. Invited and peer-reviewed.
  DOI: 10.1007/s10009-021-00637-9
• Galeana, H. R., Rajsbaum, S., Schmid, U. (2022). Continuous Tasks and the Asynchronous Computability Theorem. In M. Braverman (Ed.), 13th Innovations in Theoretical Computer Science Conference (ITCS’22) (pp. 73:1-73:27). Schloss Dagstuhl - Leibniz-Zentrum für Informatik.
  DOI: 10.4230/LIPIcs.ITCS.2022.73 / Project: ByzDEL
• Ferdowsi, A., Maier, J., Öhlinger, D., Schmid, U. (2022). A Simple Hybrid Model for Accurate Delay Modeling of a Multi-Input Gate. In 2022 Design, Automation Test in Europe Conference Exhibition (DATE) (pp. 1461–1466).
  DOI: 10.23919/DATE54114.2022.9774547 / Project: DMAC
• Ferdowsi, A. (2022). An Integer Programming Approach Reinforced by a Message-passing Procedure for Detecting Dense Attributed Subgraphs. In M. Ganzha, L. Maciaszek, M. Paprzycki, D. Ślęzak (Eds.), Proceedings of the 17th Conference on Computer Science and Intelligence Systems (pp. 569–576). Peer-reviewed.
  DOI: 10.15439/2022F64
• Nikfam, F., Marchisio, A., Martina, M., Shafique, M. (2022). AccelAT: A Framework for Accelerating the Adversarial Training of Deep Neural Networks Through Accuracy Gradient. IEEE Access, 10, 108997–109007. Peer-reviewed.
  DOI: 10.1109/ACCESS.2022.3213734
• Marchisio, A., Caramia, G., Martina, M., Shafique, M. (2022). fakeWeather: Adversarial Attacks for Deep Neural Networks Emulating Weather Conditions on the Camera Lens of Autonomous Systems. In Proceedings 2022 International Joint Conference on Neural Networks (IJCNN) (pp. 1–9).
  DOI: 10.1109/IJCNN55064.2022.9892612
• Hanif, M. A., Sarda, G. M., Marchisio, A., Masera, G., Martina, M., Shafique, M. (2022). CoNLoCNN: Exploiting Correlation and Non-Uniform Quantization for Energy-Efficient Low-precision Deep Convolutional Neural Networks. In 2Proceedings 2022 International Joint Conference on Neural Networks (IJCNN) (pp. 1–8).
  DOI: 10.1109/IJCNN55064.2022.9892902
• Marchisio, A., Bussolino, B., Salvati, E., Martina, M., Masera, G., Shafique, M. (2022). Enabling Capsule Networks at the Edge through Approximate Softmax and Squash Operations. In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (pp. 1–6).
  DOI: 10.1145/3531437.3539717
• Dave, S., Marchisio, A., Hanif, M. A., Guesmi, A., Shrivastava, A., Alouani, I., Shafique, M. (2022). Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems. In Proceedings 2022 IEEE 40th VLSI Test Symposium (VTS) (pp. 1–14). Invited.
  DOI: 10.1109/VTS52500.2021.9794253
• Shafique, M., Prabakaran, B. S. (2022). Architectures for Multimedia Processing: A Cross-Layer Perspective. In A. Chattopadhyay (Ed.), Handbook of Computer Architecture (pp. 1–22). Springer.
  DOI: 10.1007/978-981-15-6401-7_7-1
• Bhatti, I. T., Naseer, M., Shafique, M., Hasan, O. (2022). A formal approach to identifying the impact of noise on neural networks. Communications of the ACM, 65(11), 70–73. Peer-reviewed.
  DOI: 10.1145/3550492
• Putra, R. V. W., Hanif, M. A., Shafique, M. (2022). SoftSNN: Low-Cost Fault Tolerance for Spiking Neural Network Accelerators under Soft Errors. In DAC ’22: Proceedings of the 59th ACM/IEEE Design Automation Conference (pp. 151–156).
  DOI: 10.1145/3489517.3530657
• Putra, R. V. W., Hanif, M. A., Shafique, M. (2022). EnforceSNN: Enabling resilient and energy-efficient spiking neural network inference considering approximate DRAMs for embedded systems. Frontiers in Neuroscience, 16. Peer-reviewed.
  DOI: 10.3389/fnins.2022.937782
• Wicaksana Putra, R. V., Shafique, M. (2022). lpSpikeCon: Enabling Low-Precision Spiking Neural Network Processing for Efficient Unsupervised Continual Learning on Autonomous Agents. In Proceedings 2022 International Joint Conference on Neural Networks (IJCNN) (pp. 1–8).
  DOI: 10.1109/IJCNN55064.2022.9892948
• Ahmadi, M. M., Alrahis, L., Colucci, A., Sinanoglu, O., Shafique, M. (2022). NeuroUnlock: Unlocking the Architecture of Obfuscated Deep Neural Networks. In Proceedings 2022 International Joint Conference on Neural Networks (IJCNN) (pp. 01–10).
  DOI: 10.1109/IJCNN55064.2022.9892545
• Colucci, A., Steininger, A., Shafique, M. (2022). enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks. In Proceedings 2022 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS) (pp. 5155–5162).
  DOI: 10.1109/IROS47612.2022.9982181
• van Ditmarsch, H., Fruzsa, K., Kuznets, R. (2022). A new hope. In D. Fernández-Duque, A. PALMIGIANO, S. Pinchinat (Eds.), Advances in Modal Logic, Volume 14 (pp. 349–369). College Publications. Peer-reviewed.
  DOI: 10.34726/2821 / Download: PDF / Project: ByzDEL
• Függer, M., Lenzen, C., Schmid, U. (2022). On Specifications and Proofs of Timed Circuits. In J.-F. Raskin, K. Chatterjee, L. Doyen, R. Mayumdar (Eds.), Principles of Systems Design : Essays Dedicated to Thomas A. Henzinger on the Occasion of His 60th Birthday (Vol. 13660, pp. 107–130). Springer.
  DOI: 10.1007/978-3-031-22337-2 / Project: DMAC

2021

• Maier, J. (2021). Gain and Pain of a Reliable Delay Model. In Proceedings 2021 24th Euromicro Conference on Digital System Design DSD 2021 (pp. 246–250).
  DOI: 10.34726/1681 / Download: PDF / Project: DMAC
• Kuznets, R., Marin, S., Straßburger, L. (2021). Justification logic for constructive modal logic. Journal of Applied Logics, 8(8), 2313–2332. Peer-reviewed.
  DOI: 10.34726/2943 / Download: PDF / Projects: ZK 35-G, ByzDEL, ,
• Maier, J., Öhlinger, D., Schmid, U., Függer, M., Nowak, T. (2021). A Composable Glitch-Aware Delay Model. In GLSVLSI ’21: Proceedings of the 2021 Great Lakes Symposium on VLSI (pp. 147–154). Association for Computing Machinery.
  DOI: 10.1145/3453688.3461519 / Downloads: MP4, PDF / Projects: DMAC, ADynNet
• van der Giessen, I., Jalali, R., Kuznets, R. (2021). Uniform interpolation via nested sequents and hypersequents. arXiv.
  DOI: 10.48550/arXiv.2105.10930
• Dür, W., Függer, M., Steininger, A. (2021). Generation of a fault-tolerant clock through redundant crystal oscillators. Microelectronics Reliability, 120, 1–11. Peer-reviewed.
  DOI: 10.1016/j.microrel.2021.114088 / Download: PDF
• Zeiner, M., Schmid, U., Chatterjee, K. (2021). Optimal strategies for selecting coordinators. Discrete Applied Mathematics, 289, 392–415. Peer-reviewed.
  DOI: 10.1016/j.dam.2020.10.022
• Dür, W., Függer, M., Steininger, A. (2021). Generation of a fault-tolerant clock through redundant crystal oscillators. Microelectronics Reliability, 120(114088), 114088. Peer-reviewed.
  DOI: 10.1016/j.microrel.2021.114088
• Kuznets, R., Lellmann, B. (2021). Interpolation for intermediate logics via injective nested sequents. Journal of Logic and Computation, 31(3), 797–831. Peer-reviewed.
  DOI: 10.1093/logcom/exab015 / Project: ByzDEL
• Sabir, D., Hanif, M. A., Hassan, A., Rehman, S., Shafique, M. (2021). Weight Quantization Retraining for Sparse and Compressed Spatial Domain Correlation Filters. Electronics, 10(3), 351. Peer-reviewed.
  DOI: 10.3390/electronics10030351
• Sabir, D., Hanif, M. A., Hassan, A., Rehman, S., Shafique, M. (2021). TiQSA: Workload Minimization in Convolutional Neural Networks Using Tile Quantization and Symmetry Approximation. IEEE Access, 9, 53647–53668. Peer-reviewed.
  DOI: 10.1109/access.2021.3069906
• Shrivastava, N., Hanif, M. A., Mittal, S., Sarangi, S. R., Shafique, M. (2021). A survey of hardware architectures for generative adversarial networks. The Journal of Systems Architecture: Embedded Software Design, 118(102227), 102227. Peer-reviewed.
  DOI: 10.1016/j.sysarc.2021.102227
• Marchisio, A., Mrazek, V., Hanif, M. A., Shafique, M. (2021). FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29(4), 716–729. Peer-reviewed.
  DOI: 10.1109/tvlsi.2021.3059518
• Prabakaran, B. S., Akhtar, A., Rehman, S., Hasan, O., Shafique, M. (2021). BioNetExplorer: Architecture-Space Exploration of Biosignal Processing Deep Neural Networks for Wearables. IEEE Internet of Things Journal, 8(17), 13251–13265. Peer-reviewed.
  DOI: 10.1109/jiot.2021.3065815
• Odetola, T. A., Khalid, F., Mohammed, H., Sandefur, T. C., Hasan, S. R. (2021). FeSHI: Feature Map-Based Stealthy Hardware Intrinsic Attack. IEEE Access, 9, 115370–115387. Peer-reviewed.
  DOI: 10.1109/access.2021.3104520
• Putra, R. V. W., Hanif, M. A., Shafique, M. (2021). ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29(4), 702–715. Peer-reviewed.
  DOI: 10.1109/tvlsi.2021.3060509
• Maier, J., Hartl-Nesic, C., Steininger, A. (2021). Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses. IEEE Transactions on Circuits and Systems I: Regular Papers, 69(3), 1013–1026. Peer-reviewed.
  DOI: 10.1109/tcsi.2021.3130349
• Alrahis, L., Patnaik, S., Hanif, M. A., Saleh, H., Shafique, M., Sinanoglu, O. (2021). GNNUnlock+: A Systematic Methodology for Designing Graph Neural Networks-based Oracle-less Unlocking Schemes for Provably Secure Logic Locking. IEEE Transactions on Emerging Topics in Computing, 10(3), 1575–1592. Peer-reviewed.
  DOI: 10.1109/tetc.2021.3108487
• Bringmann, O., Ecker, W., Feldner, I., Frischknecht, A., Gerum, C., Hämäläinen, T., Hanif, M. A., Klaiber, M., Mueller-Gritschneder, D., Prebeck, S., Shafique, M. (2021). Automated HW/SW co-design for edge AI : state, challenges and steps ahead. In Proceedings of the 2021 International Conference on Hardware/Software Codesign and System Synthesis. 2021 International Conference on Hardware/Software Codesign and System Synthesis, Virtual Conference, Unknown. Association for Computing Machinery, New York, NY, United States.
  DOI: 10.1145/3478684.3479261
• Sekanina, L., Shafique, M., Krstic, M., Steininger, A., Stojanovic, G. (2021). Foreword. In 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE.
  DOI: 10.1109/ddecs52668.2021.9417019
• Colucci, A., Juhasz, D., Mosbeck, M., Marchisio, A., Rehman, S., Kreutzer, M., Nadbath, G., Jantsch, A., Shafique, M. (2021). MLComp: A Methodology for Machine Learning-based Performance Estimation and Adaptive Selection of Pareto-Optimal Compiler Optimization Sequences. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2021 Design, Automation Test in Europe, Online, Unknown. Peer-reviewed.
  DOI: 10.23919/date51398.2021.9474158
• Stoilkovska, I., Konnov, I., Widder, J., Zuleger, F. (2021). Eliminating Message Counters in Synchronous Threshold Automata. In VMCAI 2021: Verification, Model Checking, and Abstract Interpretation (pp. 196–218). Springer LNCS. Peer-reviewed.
  DOI: 10.1007/978-3-030-67067-2_10
• Schwarz, M., Schmid, U. (2021). Round-Oblivious Stabilizing Consensus in Dynamic Networks. In Stabilization, Safety, and Security of Distributed Systems 23rd International Symposium, SSS 2021, Virtual Event, November 17–20, 2021, Proceedings (pp. 154–172). Springer.
  DOI: 10.1007/978-3-030-91081-5_11
• Winkler, K., Schmid, U., Nowak, T. (2021). Valency-Based Consensus Under Message Adversaries Without Limit-Closure. In Fundamentals of Computation Theory (pp. 457–474). Springer. Peer-reviewed.
  DOI: 10.1007/978-3-030-86593-1_32
• Fruzsa, K., Kuznets, R., Schmid, U. (2021). Fire! In Electronic Proceedings in Theoretical Computer Science (pp. 139–153). Electronic Proceedings in Theoretical Computer Science. Peer-reviewed.
  DOI: 10.4204/eptcs.335.13 / Project: ByzDEL
• van der Giessen, I., Jalali, R., Kuznets, R. (2021). Uniform Interpolation via Nested Sequents. In Logic, Language, Information, and Computation (pp. 337–354). Lecture Notes in Computer Science. Peer-reviewed.
  DOI: 10.1007/978-3-030-88853-4_21 / Project: ByzDEL
• Alrahis, L., Patnaik, S., Khalid, F., Hanif, M. A., Saleh, H., Shafique, M., Sinanoglu, O. (2021). GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2021 Design, Automation Test in Europe, Online, Unknown. Peer-reviewed.
  DOI: 10.23919/date51398.2021.9474039
• Hanif, M. A., Shafique, M. (2021). DNN-Life: An Energy-Efficient Aging Mitigation Framework for Improving the Lifetime of On-Chip Weight Memories in Deep Neural Network Hardware Architectures. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2021 Design, Automation Test in Europe, Online, Unknown. Peer-reviewed.
  DOI: 10.23919/date51398.2021.9473943
• Hoang, L.-H., Hanif, M. A., Shafique, M. (2021). TRe-Map: Towards Reducing the Overheads of Fault-Aware Retraining of Deep Neural Networks by Merging Fault Maps. In 2021 24th Euromicro Conference on Digital System Design (DSD). 2021 24th Euromicro Conference on Digital System Design, Virtual Conference, Unknown. Peer-reviewed.
  DOI: 10.1109/dsd53832.2021.00072
• Bosio, A., O´Connor, I., Traiola, M., Echavarria, J., Teich, J., Hanif, M. A., Shafique, M., Hamdioui, S., Deveautour, B., Girard, P., Bertels, K. (2021). Emerging Computing Devices: Challenges and Opportunities for Test and Reliability. In 2021 IEEE European Test Symposium (ETS). 2021 IEEE European Test Symposium (ETS), Virtual Conference, Unknown.
  DOI: 10.1109/ets50041.2021.9465409
• Alrahis, L., Patnaik, S., Hanif, M. A., Shafique, M., Sinanoglu, O. (2021). UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction. In 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). 2021 International Conference On Computer-Aided Design, Virtual Conference, Unknown. Peer-reviewed.
  DOI: 10.1109/iccad51958.2021.9643476
• El-Allami, R., Marchisio, A., Shafique, M., Alouani, I. (2021). Securing Deep Spiking Neural Networks against Adversarial Attacks through Inherent Structural Parameters. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2021 Design, Automation Test in Europe, Online, Unknown. Peer-reviewed.
  DOI: 10.23919/date51398.2021.9473981
• Shafique, M., Marchisio, A., Wicaksana Putra, R. V., Hanif, M. A. (2021). Towards Energy-Efficient and Secure Edge AI: A Cross-Layer Framework ICCAD Special Session Paper. In 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). 2021 International Conference On Computer-Aided Design, Virtual Conference, Unknown.
  DOI: 10.1109/iccad51958.2021.9643539
• Marchisio, A., Pira, G., Martina, M., Masera, G., Shafique, M. (2021). DVS-Attacks: Adversarial Attacks on Dynamic Vision Sensors for Spiking Neural Networks. In 2021 International Joint Conference on Neural Networks (IJCNN). 2021 International Joint Conference on Neural Networks, Virtual Conference, Unknown. Peer-reviewed.
  DOI: 10.1109/ijcnn52387.2021.9534364
• Viale, A., Marchisio, A., Martina, M., Masera, G., Shafique, M. (2021). CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor. In 2021 International Joint Conference on Neural Networks (IJCNN). 2021 International Joint Conference on Neural Networks, Virtual Conference, Unknown. Peer-reviewed.
  DOI: 10.1109/ijcnn52387.2021.9533738
• Marchisio, A., Pira, G., Martina, M., Masera, G., Shafique, M. (2021). R-SNN: An Analysis and Design Methodology for Robustifying Spiking Neural Networks against Adversarial Attacks through Noise Filters for Dynamic Vision Sensors. In 2021 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS). 2021 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), Virtual Conference, Unknown. Peer-reviewed.
  DOI: 10.1109/iros51168.2021.9636718
• Adeyemo, A., Khalid, F., Odetola, T., Hasan, S. R. (2021). Security Analysis of Capsule Network Inference using Horizontal Collaboration. In 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Virtual Conference, Unknown. Peer-reviewed.
  DOI: 10.1109/mwscas47672.2021.9531833
• Putra, R. V. W., Hanif, M. A., Shafique, M. (2021). SparkXD: A Framework for Resilient and Energy-Efficient Spiking Neural Network Inference using Approximate DRAM. In 2021 58th ACM/IEEE Design Automation Conference (DAC). 2021 58th ACM/IEEE Design Automation Conference (DAC), San Francisco, California, USA, United States of America (the). Peer-reviewed.
  DOI: 10.1109/dac18074.2021.9586332
• Putra, R. V. W., Shafique, M. (2021). SpikeDyn: A Framework for Energy-Efficient Spiking Neural Networks with Continual and Unsupervised Learning Capabilities in Dynamic Environments. In 2021 58th ACM/IEEE Design Automation Conference (DAC). 2021 58th ACM/IEEE Design Automation Conference (DAC), San Francisco, California, USA, United States of America (the). Peer-reviewed.
  DOI: 10.1109/dac18074.2021.9586281
• Wicaksana Putra, R. V., Hanif, M. A., Shafique, M. (2021). ReSpawn: Energy-Efficient Fault-Tolerance for Spiking Neural Networks considering Unreliable Memories. In 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). 2021 International Conference On Computer-Aided Design, Virtual Conference, Unknown. Peer-reviewed.
  DOI: 10.1109/iccad51958.2021.9643524
• Putra, R. V. W., Shafique, M. (2021). Q-SpiNN: A Framework for Quantizing Spiking Neural Networks. In 2021 International Joint Conference on Neural Networks (IJCNN). 2021 International Joint Conference on Neural Networks, Virtual Conference, Unknown. Peer-reviewed.
  DOI: 10.1109/ijcnn52387.2021.9534087
• Tauner, S., Telesklav, M. (2021). Comparative Analysis and Enhancement of CFG-based Hardware-Assisted CFI Schemes. In ACM Transactions on Embedded Computing Systems (pp. 1–25). Association for Computing Machinery. Peer-reviewed.
  DOI: 10.1145/3476989
• Tabassam, Z., Behal, P., Najvirt, R., Steininger, A. (2021). Input/Output-Interlocking for Fault Mitigation in QDI Pipelines. In 2021 Austrochip Workshop on Microelectronics (Austrochip) (pp. 17–20). Peer-reviewed.
  DOI: 10.34726/3943 / Download: PDF
• Behal, P., Huemer, F., Najvirt, R., Tabassam, Z., Steininger, A. (2021). Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. In 2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) (pp. 25–33). IEEE. Peer-reviewed.
  DOI: 10.34726/3945 / Download: PDF
• Behal, P., Huemer, F. F., Najvirt, R., Steininger, A. (2021). An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. In 2021 24th Euromicro Conference on Digital System Design (DSD). 24th Euromicro Conference on Digital System Design, Palermo, Italy. Peer-reviewed.
  DOI: 10.34726/4044 / Download: PDF
• Elshehaby, R., Steininger, A. (2021). Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines. In 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS). 24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Wien, Austria. Ieee Cs. Peer-reviewed.
  DOI: 10.34726/4046 / Download: PDF

2020

• Stoilkovska, I., Konnov, I., Widder, J., Zuleger, F. (2020). Eliminating Message Counters in Threshold Automata. In Automated Technology for Verification and Analysis. 18th International Symposium, ATVA 2020, Hanoi, Vietnam, October 19-23, 2020, Proceedings (pp. 192–212). Springer. Peer-reviewed.
  DOI: 10.34726/423 / Download: PDF
• Öhlinger, D., Maier, J., Függer, M., Schmid, U. (2020). The involution tool for accurate digital timing and power analysis. Integration, 76, 87–98. Peer-reviewed.
  DOI: 10.1016/j.vlsi.2020.09.007 / Download: PDF / Project: DMAC
• Capra, M., Bussolino, B., Marchisio, A., Shafique, M., Masera, G., Martina, M. (2020). An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks. Future Internet, 12(7), Article 113. Peer-reviewed.
  DOI: 10.3390/fi12070113 / Download: PDF
• Konnov, I., Lazic, M., Stoilkovska, I., Widder, J. (2020). Tutorial: Parameterized Verification with Byzantine Model Checker. In Formal Techniques for Distributed Objects, Components, and Systems. 40th IFIP WG 6.1 International Conference, FORTE 2020, Held as Part of the 15th International Federated Conference on Distributed Computing Techniques, DisCoTec 2020, Valletta, Malta, June 15–19, 2020, Proceedings (pp. 189–207). Springer. Invited and peer-reviewed.
  DOI: 10.34726/422 / Download: PDF
• Theocharides, T., Shafique, M., Choi, J., Mutlu, O. (2020). Guest Editorial: Robust Resource-Constrained Systems for Machine Learning. IEEE DESIGN TEST, 37(2), 5–7.
  DOI: 10.1109/mdat.2020.2971201
• Függer, M., Najvirt, R., Nowak, T., Schmid, U. (2020). A Faithful Binary Circuit Model. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(10), 2784–2797. Peer-reviewed.
  DOI: 10.1109/tcad.2019.2937748
• Otepka, J., Mandlburger, G., Schütz, M., Pfeifer, N., Wimmer, M. (2020). Efficient Loading And Visualization Of Massive Feature-Rich Point Clouds Without Hierarchical Acceleration Structures. In XXIV ISPRS Congress, Commission II (pp. 293–300).
  DOI: 10.5194/isprs-archives-xliii-b2-2020-293-2020
• Ali, H., Khalid, F., Tariq, H. A., Hanif, M. A., Ahmed, R., Rehman, S. (2020). SSCNets: Robustifying DNNs using Secure Selective Convolutional Filters. IEEE Design and Test, 37(2), 58–65. Peer-reviewed.
  DOI: 10.1109/mdat.2019.2961325
• Achararit, P., Hanif, M. A., Putra, R. V. W., Shafique, M., Hara-Azumi, Y. (2020). APNAS: Accuracy-and-Performance-Aware Neural Architecture Search for Neural Hardware Accelerators. IEEE Access, 8, 165319–165334. Peer-reviewed.
  DOI: 10.1109/access.2020.3022327
• Hanif, M. A., Manglik, A., Shafique, M. (2020). Resistive Crossbar-Aware Neural Network Design and Optimization. IEEE Access, 8, 229066–229085. Peer-reviewed.
  DOI: 10.1109/access.2020.3045071
• Ayub, M. K., Hanif, M. A., Hasan, O., Shafique, M. (2020). PEAL: Probabilistic Error Analysis Methodology for Low-power Approximate Adders. ACM Journal on Emerging Technologies in Computing Systems, 17(1), 1–37. Peer-reviewed.
  DOI: 10.1145/3405430
• Ahmad, H., Arif, T., Hanif, M. A., Hafiz, R., Shafique, M. (2020). SuperSlash: A Unified Design Space Exploration and Model Compression Methodology for Design of Deep Learning Accelerators With Reduced Off-Chip Memory Access Volume. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(11), 4191–4204. Peer-reviewed.
  DOI: 10.1109/tcad.2020.3012865
• Capra, M., Bussolino, B., Marchisio, A., Masera, G., Martina, M., Shafique, M. (2020). Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead. IEEE Access, 8, 225134–225180. Peer-reviewed.
  DOI: 10.1109/access.2020.3039858
• Marchisio, A., Mrazek, V., Hanif, M. A., Shafique, M. (2020). DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40(9), 1768–1781. Peer-reviewed.
  DOI: 10.1109/tcad.2020.3030610
• Khalid, F., Hasan, S. R., Hasan, O., Shafique, M. (2020). SIMCom: Statistical Sniffing of Inter-Module Communications for Runtime Hardware Trojan Detection. Microprocessors and Microsystems, 77(103122), 103122. Peer-reviewed.
  DOI: 10.1016/j.micpro.2020.103122
• Khalid, F., Hasan, S. R., Zia, S., Hasan, O., Awwad, F., Shafique, M. (2020). MacLeR: Machine Learning-Based Runtime Hardware Trojan Detection in Resource-Constrained IoT Edge Devices. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(11), 3748–3761. Peer-reviewed.
  DOI: 10.1109/tcad.2020.3012236
• Khdr, H., Shafique, M., Pagani, S., Herkersdorf, A., Henkel, J. (2020). Combinatorial Auctions for Temperature-Constrained Resource Management in Manycores. IEEE Transactions on Parallel and Distributed Systems, 31(7), 1605–1620. Peer-reviewed.
  DOI: 10.1109/tpds.2020.2965523
• Putra, R. V. W., Shafique, M. (2020). FSpiNN: An Optimization Framework for Memory-Efficient and Energy-Efficient Spiking Neural Networks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(11), 3601–3613. Peer-reviewed.
  DOI: 10.1109/tcad.2020.3013049
• Nomani, T., Mohsin, M., Pervaiz, Z., Shafique, M. (2020). xUAVs: Towards Efficient Approximate Computing for UAVs-Low Power Approximate Adders With Single LUT Delay for FPGA-Based Aerial Imaging Optimization. IEEE Access, 8, 102982–102996. Peer-reviewed.
  DOI: 10.1109/access.2020.2998957
• Riaz, M., Hafiz, R., Khaliq, S. A., Faisal, M., Iqbal, H. T., Ali, M., Shafique, M. (2020). CAxCNN: Towards the Use of Canonic Sign Digit Based Approximation for Hardware-Friendly Convolutional Neural Networks. IEEE Access, 8, 127014–127021. Peer-reviewed.
  DOI: 10.1109/access.2020.3008256
• Ansari, M., Salehi, M., Safari, S., Ejlali, A., Shafique, M. (2020). Peak-Power-Aware Primary-Backup Technique for Efficient Fault-Tolerance in Multicore Embedded Systems. IEEE Access, 8, 142843–142857. Peer-reviewed.
  DOI: 10.1109/access.2020.3013721
• Shafique, M., Naseer, M., Theocharides, T., Kyrkou, C., Mutlu, O., Orosa, L., Choi, J. (2020). Robust Machine Learning Systems: Challenges,Current Trends, Perspectives, and the Road Ahead. IEEE Design and Test, 37(2), 30–57. Peer-reviewed.
  DOI: 10.1109/mdat.2020.2971217
• Rathore, V., Chaturvedi, V., Singh, A. K., Srikanthan, T., Shafique, M. (2020). Longevity Framework: Leveraging Online Integrated Aging-Aware Hierarchical Mapping and VF-Selection for Lifetime Reliability Optimization in Manycore Processors. IEEE Transactions on Computers, 70(7), 1106–1119. Peer-reviewed.
  DOI: 10.1109/tc.2020.3006571
• Yahya, Z., Hassan, M., Younis, S., Shafique, M. (2020). Probabilistic Analysis of Targeted Attacks Using Transform-Domain Adversarial Examples. IEEE Access, 8, 33855–33869. Peer-reviewed.
  DOI: 10.1109/access.2020.2974525
• Függer, M., Nowak, T., Winkler, K. (2020). On the radius of nonsplit graphs and information dissemination in dynamic networks. Discrete Applied Mathematics, 282, 257–264. Peer-reviewed.
  DOI: 10.1016/j.dam.2020.02.013
• Pavlogiannis, A., Schaumberger, N., Schmid, U., Chatterjee, K. (2020). Precedence-Aware Automated Competitive Analysis of Real-Time Scheduling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(11), 3981–3992. Peer-reviewed.
  DOI: 10.1109/tcad.2020.3012803
• Zeiner, M., Schmid, U. (2020). Upper and Lower Bounds for the Synchronizer Performance in Systems with Probabilistic Message Loss. Methodology and Computing in Applied Probability, 23(3), 1023–1056. Peer-reviewed.
  DOI: 10.1007/s11009-020-09792-z
• Herkersdorf, A., Engel, M., Glaß, M., Henkel, J., Kleeberger, V. B., Kühn, J. M., Marwedel, P., Mueller-Gritschneder, D., Nassif, S. R., Rehman, S., Rosenstiel, W., Schlichtmann, U., Shafique, M., Teich, J., Wehn, N., Weis, C. (2020). RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience. In J. Henkel N. Dutt (Eds.), Dependable Embedded Systems (pp. 1–27). Springer Nature Switzerland AG. Peer-reviewed.
  DOI: 10.1007/978-3-030-52017-5_1
• Kriebel, F., Chen, K.-H., Rehman, S., Henkel, J., Chen, J.-J., Shafique, M. (2020). Dependable Software Generation and Execution on Embedded Systems. In J. Henkel N. Dutt (Eds.), Dependable Embedded Systems (pp. 139–160). Springer Nature Switzerland AG. Peer-reviewed.
  DOI: 10.1007/978-3-030-52017-5_6
• Kriebel, F., Khalid, F., Prabakaran, B. S., Rehman, S., Shafique, M. (2020). Fault-Tolerant Computing with Heterogeneous Hardening Modes. In J. Henkel N. Dutt (Eds.), Dependable Embedded Systems (pp. 161–180). Springer Nature Switzerland AG. Peer-reviewed.
  DOI: 10.1007/978-3-030-52017-5_7
• Salehi, M., Kriebel, F., Rehman, S., Shafique, M. (2020). Power-Aware Fault-Tolerance for Embedded Systems. In J. Henkel N. Dutt (Eds.), Dependable Embedded Systems (pp. 565–588). Springer Nature Switzerland AG. Peer-reviewed.
  DOI: 10.1007/978-3-030-52017-5_24
• Hanif, M. A., Khalid, F., Putra, R. V. W., Teimoori, M. T., Kriebel, F., Zhang, J. (Jun), Liu, K., Rehman, S., Theocharides, T., Artusi, A., Garg, S., Shafique, M. (2020). Robust Computing for Machine Learning-Based Systems. In J. Henkel N. Dutt (Eds.), Dependable Embedded Systems (pp. 479–503). Springer Nature Switzerland AG. Peer-reviewed.
  DOI: 10.1007/978-3-030-52017-5_20
• Marchisio, A., Bussolino, B., Colucci, A., Martina, M., Masera, G., Shafique, M. (2020). Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks. In Proceedings of 2020 57th ACM/IEEE Design Automation Conference (DAC) (pp. 1–6). IEEE. Peer-reviewed.
  HDL: 20.500.12708/55581
• Marchisio, A., Bussolino, B., Colucci, A., Hanif, M. A., Martina, M., Masera, G., Shafique, M. (2020). FasTrCaps: An Integrated Framework for Fast yet Accurate Training of Capsule Networks. In Proceedings of 2020 International Joint Conference on Neural Networks (IJCNN) (pp. 1–8). IEEE. Peer-reviewed.
  HDL: 20.500.12708/55582
• Marchisio, A., Nanfa, G., Khalid, F., Hanif, M. A., Martina, M., Shafique, M. (2020). Is Spiking Secure? A Comparative Study on the Security Vulnerabilities of Spiking and Deep Neural Networks. In Proceedings of 2020 International Joint Conference on Neural Networks (IJCNN) (pp. 1–8). IEEE. Peer-reviewed.
  HDL: 20.500.12708/55583
• Brandalero, M., Lignati, B. N., Beck, A. C. S., Shafique, M., Hübner, M. (2020). Proactive Aging Mitigation in CGRAs through Utilization-Aware Allocation. In Proceedings of 2020 57th ACM/IEEE Design Automation Conference (DAC) (pp. 1–6). IEEE. Peer-reviewed.
  HDL: 20.500.12708/55584
• Morid Ahmadi, M., Khalid, F., Shafique, M. (2020). Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities. In Proceedings of the Fifth International Conferenceon Cyber-Technologies and Cyber-Systems (pp. 1–6). Peer-reviewed.
  HDL: 20.500.12708/55599
• Khalid, F., Hanif, M. A., Shafique, M. (2020). Exploiting Vulnerabilities in Deep Neural Networks: Adversarial and Fault-Injection Attacks. In Proceedings of the Fifth International Conferenceon Cyber-Technologies and Cyber-Systems (pp. 24–29). Peer-reviewed.
  HDL: 20.500.12708/55602
• Brunvand, E., Stevens, K., Moreira, M., Steininger, A. (2020). Welcome Message: ASYNC 2020. In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE Computer Society.
  DOI: 10.1109/async49171.2020.00005
• Hanif, M. A., Hafiz, R., Hasan, O., Shafique, M. (2020). PEMACx: A Probabilistic Error Analysis Methodology for Adders with Cascaded Approximate Units. In 2020 57th ACM/IEEE Design Automation Conference (DAC). 2020 57th ACM/IEEE Design Automation Conference (DAC), San Francisco, United States of America (the). IEEE. Peer-reviewed.
  DOI: 10.1109/dac18072.2020.9218678
• Hanif, M. A., Shafique, M. (2020). Dependable Deep Learning: Towards Cost-Efficient Resilience of Deep Neural Network Accelerators against Soft Errors and Permanent Faults. In 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS). 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), Napoli, Italy. IEEE. Peer-reviewed.
  DOI: 10.1109/iolts50870.2020.9159734
• Hanif, M. A., Hoang, L.-H., Shafique, M. (2020). Cross-layer approaches for improving the dependability of deep learning systems. In Proceedings of the 23th International Workshop on Software and Compilers for Embedded Systems. 2020 23th International Workshop on Software and Compilers for Embedded Systems (SCOPES), St. Goar, Germany. ACM. Peer-reviewed.
  DOI: 10.1145/3378678.3391884
• Marchisio, A., Mrazek, V., Hanif, M. A., Shafique, M. (2020). ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations. In 2020 Design, Automation Test in Europe Conference Exhibition (DATE). 2020 Design, Automation Test in Europe Conference Exhibition (DATE), Grenoble, France. IEEE. Peer-reviewed.
  DOI: 10.23919/date48585.2020.9116393
• Marchisio, A., Massa, A., Mrazek, V., Bussolino, B., Martina, M., Shafique, M. (2020). NASCaps. In Proceedings of the 39th International Conference on Computer-Aided Design. 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), Virtual Conference, Austria. IEEE. Peer-reviewed.
  DOI: 10.1145/3400302.3415731
• Cignarale, G., Primiero, G. (2020). A Multi-Agent Depth Bounded Boolean Logic. In Software Engineering and Formal Methods. SEFM 2020 Collocated Workshops (pp. 176–191). Peer-reviewed.
  DOI: 10.1007/978-3-030-67220-1_14 / Project: ByzDEL
• Schlögl, T., Schmid, U., Kuznets, R. (2020). The Persistence of False Memory: Brain in a Vat despite Perfect Clocks. In PRIMA 2020: Principles and Practice of Multi-Agent Systems (pp. 403–411). Springer Nature Switzerland AG. Peer-reviewed.
  DOI: 10.1007/978-3-030-69322-0_30 / Project: ByzDEL
• Venceslai, V., Marchisio, A., Alouani, I., Martina, M., Shafique, M. (2020). NeuroAttack: Undermining Spiking Neural Networks Security through Externally Triggered Bit-Flips. In 2020 International Joint Conference on Neural Networks (IJCNN). 2020 International Joint Conference on Neural Networks (IJCNN), Glasgow, United Kingdom of Great Britain and Northern Ireland (the). IEEE. Peer-reviewed.
  DOI: 10.1109/ijcnn48605.2020.9207351
• Massa, R., Marchisio, A., Martina, M., Shafique, M. (2020). An Efficient Spiking Neural Network for Recognizing Gestures with a DVS Camera on the Loihi Neuromorphic Processor. In 2020 International Joint Conference on Neural Networks (IJCNN). 2020 International Joint Conference on Neural Networks (IJCNN), Glasgow, United Kingdom of Great Britain and Northern Ireland (the). IEEE. Peer-reviewed.
  DOI: 10.1109/ijcnn48605.2020.9207109
• Colucci, A., Marchisio, A., Bussolino, B., Mrazek, V., Martina, M., Masera, G., Shafique, M. (2020). A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress. In 2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). 2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS), Virtual Conference, Austria. IEEE. Peer-reviewed.
  DOI: 10.1109/codesisss51650.2020.9244038
• Prabakaran, B. S., Garcia Jimenez, A., Martinez, G. M., Shafique, M. (2020). EMAP: A Cloud-Edge Hybrid Framework for EEG Monitoring and Cross-Correlation Based Real-time Anomaly Prediction. In 2020 57th ACM/IEEE Design Automation Conference (DAC). 2020 57th ACM/IEEE Design Automation Conference (DAC), San Francisco (Virtual), United States of America (the). IEEE. Peer-reviewed.
  DOI: 10.1109/dac18072.2020.9218713
• Prabakaran, B. S., Mrazek, V., Vasicek, Z., Sekanina, L., Shafique, M. (2020). ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. In 2020 57th ACM/IEEE Design Automation Conference (DAC). 57th ACM/IEEE Design Automation Conference (DAC2020), San Francisco (Virtual), United States of America (the). IEEE. Peer-reviewed.
  DOI: 10.1109/dac18072.2020.9218533
• Castro-Godinez, J., Shafique, M., Henkel, J. (2020). Towards Quality-Driven Approximate Software Generation for Accurate Hardware: Work-in-Progress. In 2020 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES). 2020 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Virtual Conference, Austria. IEEE. Peer-reviewed.
  DOI: 10.1109/cases51649.2020.9243814
• Castro-Godinez, J., Hernandez-Araya, D., Shafique, M., Henkel, J. (2020). Approximate Acceleration for CNN-based Applications on IoT Edge Devices. In 2020 IEEE 11th Latin American Symposium on Circuits Systems (LASCAS). 2020 IEEE 11th Latin American Symposium on Circuits Systems (LASCAS), San Jose, Costa Rica. IEEE. Peer-reviewed.
  DOI: 10.1109/lascas45839.2020.9069040
• Hernandez-Araya, D., Castro-Godinez, J., Shafique, M., Henkel, J. (2020). AUGER: A Tool for Generating Approximate Arithmetic Circuits. In 2020 IEEE 11th Latin American Symposium on Circuits Systems (LASCAS). 2020 IEEE 11th Latin American Symposium on Circuits Systems (LASCAS), San Jose, Costa Rica. IEEE. Peer-reviewed.
  DOI: 10.1109/lascas45839.2020.9069045
• Khalid, F., Ali, H., Abdullah Hanif, M., Rehman, S., Ahmed, R., Shafique, M. (2020). FaDec: A Fast Decision-based Attack for Adversarial Machine Learning. In 2020 International Joint Conference on Neural Networks (IJCNN). 2020 International Joint Conference on Neural Networks (IJCNN), Glasgow, United Kingdom of Great Britain and Northern Ireland (the). IEEE. Peer-reviewed.
  DOI: 10.1109/ijcnn48605.2020.9207635
• Hoang, L.-H., Hanif, M. A., Shafique, M. (2020). FT-ClipAct: Resilience Analysis of Deep Neural Networks and Improving their Fault Tolerance using Clipped Activation. In 2020 Design, Automation Test in Europe Conference Exhibition (DATE). 2020 Design, Automation Test in Europe Conference Exhibition (DATE), Grenoble, France. IEEE. Peer-reviewed.
  DOI: 10.23919/date48585.2020.9116571
• Naseer, M., Minhas, M. F., Khalid, F., Hanif, M. A., Hasan, O., Shafique, M. (2020). FANNet: Formal Analysis of Noise Tolerance, Training Bias and Input Sensitivity in Neural Networks. In 2020 Design, Automation Test in Europe Conference Exhibition (DATE). 2020 Design, Automation Test in Europe Conference Exhibition (DATE), Grenoble, France. IEEE. Peer-reviewed.
  DOI: 10.23919/date48585.2020.9116247
• Wicaksana Putra, R. V., Abdullah Hanif, M., Shafique, M. (2020). DRMap: A Generic DRAM Data Mapping Policy for Energy-Efficient Processing of Convolutional Neural Networks. In 2020 57th ACM/IEEE Design Automation Conference (DAC). 2020 57th ACM/IEEE Design Automation Conference (DAC), San Francisco (Virtual), United States of America (the). IEEE. Peer-reviewed.
  DOI: 10.1109/dac18072.2020.9218672
• Duer, W., Steininger, A. (2020). Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock. In 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS). 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Novi Sad, Serbia. Ieee Cs. Peer-reviewed.
  DOI: 10.1109/ddecs50862.2020.9095577
• Huemer, F. F., Steininger, A. (2020). Timing Domain Crossing using Muller Pipelines. In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 26th IEEE International Symposium on Asynchronous Circuits and Systems, Snowbird, Utah, USA, Austria. Ieee Cs. Peer-reviewed.
  DOI: 10.34726/4041 / Download: PDF
• Huemer, F. F., Steininger, A. (2020). Sorting Network based Full Adders for QDI Circuits. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. Peer-reviewed.
  DOI: 10.34726/4042 / Download: PDF
• Huemer, F. F., Najvirt, R., Steininger, A. (2020). Identification and Confinement of Fault Sensitivity Windows in QDI Logic. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. Peer-reviewed.
  DOI: 10.34726/4043 / Download: PDF
• Elshehaby, R., Steininger, A. (2020). On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective. In 2020 IEEE 38th International Conference on Computer Design (ICCD). IEEE International Conference on Computer Design, Hartford, Connecticut, USA, Austria. Peer-reviewed.
  DOI: 10.34726/4045 / Download: PDF

2019

• Kuznets, R., Straßburger, L. (2019). Maehara-style Modal Nested Calculi. Archive for Mathematical Logic, 58(3–4), 359–385. Peer-reviewed.
  DOI: 10.1007/s00153-018-0636-1
• Ratasich, D., Khalid, F., Geissler, F., Grosu, R., Shafique, M., Bartocci, E. (2019). A Roadmap Toward the Resilient Internet of Things for Cyber-Physical Systems. IEEE Access, 7, 13260–13283. Peer-reviewed.
  DOI: 10.1109/access.2019.2891969
• Zeiner, M., Schwarz, M., Schmid, U. (2019). On Linear-Time Data Dissemination in Dynamic Rooted Trees. Discrete Applied Mathematics, 255, 307–319. Peer-reviewed.
  DOI: 10.1016/j.dam.2018.08.015
• Huemer, F., Steininger, A. (2019). Novel Approaches for Efficient Delay-Insensitive Communication. Journal of Low Power Electronics and Applications, 9(2), 16. Peer-reviewed.
  DOI: 10.3390/jlpea9020016
• Winkler, K., Schmid, U. (2019). An Overview of Recent Results for Consensus in Directed Dynamic Networks. European Association for Theoretical Computer Science. Bulletin, 128, 30. Peer-reviewed.
  HDL: 20.500.12708/143248
• Winkler, K., Schwarz, M., Schmid, U. (2019). Consensus in rooted dynamic networks with short-lived stability. Distributed Computing, 32(5), 443–458. Peer-reviewed.
  DOI: 10.1007/s00446-019-00348-0
• Dinakarrao, S. M. P., Jantsch, A., Shafique, M. (2019). Computer-aided arrhythmia diagnosis with bio-signal processing: A survey of trends and techniques. ACM Computing Surveys, 52(2), 1–37. Peer-reviewed.
  DOI: 10.1145/3297711
• Paltrinieri, A., Peloso, R., Masera, G., Shafique, M., Martina, M. (2019). On the Effect of Approximate-Computing in Motion Estimation. Journal of Low Power Electronics, 15(1), 40–50. Peer-reviewed.
  DOI: 10.1166/jolpe.2019.1592
• Mazahir, S., Hasan, O., Shafique, M. (2019). Self-Compensating Accelerators for Efficient Approximate Computing. Microelectronics Journal, 88, 9–17. Peer-reviewed.
  DOI: 10.1016/j.mejo.2019.03.008
• Dinakarrao, S. M. P., Joseph, A., Haridass, A., Shafique, M., Henkel, J., Homayoun, H. (2019). Application and Thermal-reliability-aware Reinforcement Learning Based Multi-core Power Management. ACM Journal on Emerging Technologies in Computing Systems, 15(4), 1–19. Peer-reviewed.
  DOI: 10.1145/3323055
• Gillani, G. A., Hanif, M. A., Verstoep, B., Gerez, S. H., Shafique, M., Kokkeler, A. B. J. (2019). MACISH: Designing Approximate MAC Accelerators With Internal-Self-Healing. IEEE Access, 7, 77142–77160. Peer-reviewed.
  DOI: 10.1109/access.2019.2920335
• Bukhari, S. A. A., Khalid, F., Hasan, O., Shafique, M., Henkel, J. (2019). Towards Model Checking-Driven Fair Comparison of Dynamic Thermal Management Techniques under Multi-Threaded Workloads. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(8), 1725–1738. Peer-reviewed.
  DOI: 10.1109/tcad.2019.2921313
• Akbari, O., Kamal, M., Afzali-Kusha, A., Pedram, M., Shafique, M. (2019). X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(10), 2558–2571. Peer-reviewed.
  DOI: 10.1109/tcad.2019.2937738
• Amjad, R., Hafiz, R., Ilyas, M. U., Younis, M. S., Shafique, M. (2019). m-SAAC: Multi-stage Adaptive Approximation Control to Select Approximate Computing Modes for Vision Applications. Microelectronics Journal, 91, 84–91. Peer-reviewed.
  DOI: 10.1016/j.mejo.2019.07.010
• Castro-Godínez, J., Shafique, M., Henkel, J. (2019). ECAx: Balancing Error Correction Costs in Approximate Accelerators. ACM Transactions on Embedded Computing Systems, 18(5s), 1–20. Peer-reviewed.
  DOI: 10.1145/3358179
• Abdullah Hanif, M., Shafique, M. (2019). SalvageDNN: Salvaging Deep Neural Network Accelerators with Permanent Faults through Saliency-driven Fault-aware Mapping. Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences, 378(2164), 20190164. Peer-reviewed.
  DOI: 10.1098/rsta.2019.0164
• Krstic, M., Jones, I., Steininger, A., Függer, M. (2019). Special Issue “Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018.” Journal of Low Power Electronics and Applications, 9(2), 2.
  HDL: 20.500.12708/143834
• Polzer, T., Huemer, F., Steininger, A. (2019). An Experimental Study of Metastability-Induced Glitching Behavior. Journal of Circuits, Systems, and Computers, 28(supp01), 1940006. Peer-reviewed.
  DOI: 10.1142/s0218126619400061
• Schmid, U. (2019). Design and Implementation of the Bachelor with Honors Program at TU Wien. European Honors Council. Journal, 3(2). Peer-reviewed.
  DOI: 10.31378/jehc.3.2
• Kuznets, R., Studer, T. (2019). Logics of Proofs and Justifications. College Publications.
  HDL: 20.500.12708/24606
• Reda, S., Shafique, M. (Eds.). (2019). Approximate Circuits. Springer International Publishing. Peer-reviewed.
  DOI: 10.1007/978-3-319-99322-5
• Kuznets, R. (2019). Through an Inference Rule, Darkly. In S. Centrone, S. Negri, D. Sarikaya, P. Schuster (Eds.), Mathesis Universalis, Computability and Proof (pp. 131–158). Springer International Publishing. Peer-reviewed.
  DOI: 10.1007/978-3-030-20447-1_10
• Shafique, M., Hasan, O., Hafiz, R., Mazahir, S., Hanif, M. A., Rehman, S. (2019). Approximate computing across the hardware and software stacks. In Many-Core Computing: Hardware and Software (pp. 497–522). IET.
  DOI: 10.1049/pbpc022e_ch20
• Hanif, M. A., Hafiz, R., Javed, M. U., Rehman, S., Shafique, M. (2019). Energy-Efficient Design of Advanced Machine Learning Hardware. In Machine Learning in VLSI Computer-Aided Design (pp. 647–678). Springer International Publishing. Peer-reviewed.
  DOI: 10.1007/978-3-030-04666-8_21
• Hanif, M. A., Hafiz, R., Shafique, M. (2019). Configurable Models and Design Space Exploration for Low-Latency Approximate Adders. In Approximate Circuits (pp. 3–23). Springer International Publishing. Peer-reviewed.
  DOI: 10.1007/978-3-319-99322-5_1
• Rehman, S., Prabakaran, B. S., El-Harouni, W., Shafique, M., Henkel, J. (2019). Heterogeneous Approximate Multipliers: Architectures and Design Methodologies. In Approximate Circuits (pp. 45–66). Springer International Publishing. Peer-reviewed.
  DOI: 10.1007/978-3-319-99322-5_3
• Mazahir, S., Ayub, M. K., Hasan, O., Shafique, M. (2019). Probabilistic Error Analysis of Approximate Adders and Multipliers. In Approximate Circuits (pp. 99–120). Springer International Publishing. Peer-reviewed.
  DOI: 10.1007/978-3-319-99322-5_5
• Prabakaran, B. S., El-Harouni, W., Rehman, S., Shafique, M. (2019). Approximate Multi-Accelerator Tiled Architecture for Energy-Efficient Motion Estimation. In Approximate Circuits (pp. 249–268). Springer International Publishing. Peer-reviewed.
  DOI: 10.1007/978-3-319-99322-5_12
• Hanif, M. A., Javed, M. U., Hafiz, R., Rehman, S., Shafique, M. (2019). Hardware–Software Approximations for Deep Neural Networks. In Approximate Circuits (pp. 269–288). Springer International Publishing. Peer-reviewed.
  DOI: 10.1007/978-3-319-99322-5_13
• Prosperi, L., Kuznets, R., Schmid, U., Fruzsa, K., Gréaux, L. (2019). Knowledge in Byzantine Message-Passing Systems I: Framework and the Causal Cone (TUW-260549).
  HDL: 20.500.12708/39204
• Kinali, A., Lenzen, C., Perner, M. (2019). Fault-tolerant High-Performance Clock Distribution.
  HDL: 20.500.12708/39734
• Öhlinger, D., Maier, J., Függer, M., Schmid, U. (2019). The involution tool for accurate digital timing and power analysis. In 2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). 29th International Symposium on Power and Timing Modeling, Optimization and Simulation, Rhodos, Greece.
  DOI: 10.1109/PATMOS.2019.8862165 / Download: PDF
• Maier, J., Steininger, A. (2019). Efficient Metastability Characterization for Schmitt-Triggers. In 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 25th IEEE International Symposium on Asynchronous Circuits and Systems, Hirosaki, Japan.
  DOI: 10.1109/ASYNC.2019.00024 / Download: PDF
• Maier, J., Függer, M., Nowak, T., Schmid, U. (2019). Transistor-Level Analysis of Dynamic Delay Models. In 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 25th IEEE International Symposium on Asynchronous Circuits and Systems, Hirosaki, Japan. IEEE.
  DOI: 10.1109/ASYNC.2019.00019 / Download: PDF
• Rincon Galeana, H., Winkler, K., Schmid, U., Rajsbaum, S. (2019). A Topological View of Partitioning Arguments: Reducing 𝑘-Set Agreement to Consensus. In Stabilization, Safety, and Security of Distributed Systems 21st International Symposium, SSS 2019, Pisa, Italy, October 22–25, 2019, Proceedings (pp. 307–322). Lecture Notes in Computer Science / Springer. Peer-reviewed.
  DOI: 10.1007/978-3-030-34992-9_25
• Rathore, V., Chaturvedi, V., Singh, A. K., Srikanthan, T., Shafique, M. (2019). Life Guard: A Reinforcement Learning-Based Task Mapping Strategy for Performance-Centric Aging Managemen. In Proceedings of the 56th Annual Design Automation Conference 2019. 2019 56th ACM/IEEE Design Automation Conference (DAC), Las Vegas, United States of America (the). IEEE. Peer-reviewed.
  DOI: 10.1145/3316781.3317849
• Zang, J. (Jun), Liu, K., Khalid, F., Hanif, M. A., Rehman, S., Theocharides, T., Artussi, A., Shafique, M., Garg, S. (2019). Building Robust Machine Learning Systems. In Proceedings of the 56th Annual Design Automation Conference 2019. 2019 56th ACM/IEEE Design Automation Conference (DAC), Las Vegas, United States of America (the). IEEE. Peer-reviewed.
  DOI: 10.1145/3316781.3323472
• Marchisio, A., Nanfa, G., Martina, M., Shafique, M. (2019). Security Vulnerabilities of Deep, Capsule and Spiking Neural Networks against Adversarial Attacks. In Proceedings of IEEE International Workshop on Robust and Trustworthy Machine Learning (RTML) 2019 (pp. 1–4). Peer-reviewed.
  HDL: 20.500.12708/55718
• Jayanti, P., Lynch, N. A., Patt-Shamir, B., Schmid, U. (2019). 2019 Principles of Distributed Computing Doctoral Dissertation Award. In Proceedings of the 2019 ACM Symposium on Principles of Distributed Computing. ACM.
  DOI: 10.1145/3293611.3341565
• Damian, A., Drăgoi, C., Militaru, A., Widder, J. (2019). Communication-Closed Asynchronous Protocols. In Computer Aided Verification (pp. 344–363). Springer. Peer-reviewed.
  DOI: 10.1007/978-3-030-25543-5_20
• Bertrand, N., Konnov, I., Lazić, M., Widder, J. (2019). Verification of Randomized Consensus Algorithms Under Round-Rigid Adversaries. In W. Fokkink R. van Glabbeek (Eds.), 30th International Conference on Concurrency Theory (pp. 33:1-33:15). Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany. Peer-reviewed.
  DOI: 10.4230/LIPIcs.CONCUR.2019.33
• Stoilkovska, I., Konnov, I., Widder, J., Zuleger, F. (2019). Verifying Safety of Synchronous Fault-Tolerant Algorithms by Bounded Model Checking. In International Conference on Tools and Algorithms for the Construction and Analysis of Systems (pp. 357–374). Springer. Peer-reviewed.
  HDL: 20.500.12708/56804
• Kuznets, R., Prosperi, L., Schmid, U., Fruzsa, K. (2019). Epistemic Reasoning with Byzantine-Faulty Agents. In A. Herzig A. Popescu (Eds.), Frontiers of Combining Systems (pp. 259–276). Springer. Peer-reviewed.
  DOI: 10.1007/978-3-030-29007-8_15
• Fruzsa, K. (2019). Hope for Epistemic Reasoning with Faulty Agents! In ESSLLI 2019 Student Session (pp. 169–180). Peer-reviewed.
  HDL: 20.500.12708/56972
• Mrazek, V., Hanif, M. A., Vasicek, Z., Sekanina, L., Shafique, M. (2019). autoAx. In Proceedings of the 56th Annual Design Automation Conference 2019. 2019 56th ACM/IEEE Design Automation Conference (DAC), Las Vegas, United States of America (the). IEEE. Peer-reviewed.
  DOI: 10.1145/3316781.3317781
• Hanif, M. A., Khalid, F., Shafique, M. (2019). CANN. In Proceedings of the 56th Annual Design Automation Conference 2019. 2019 56th ACM/IEEE Design Automation Conference (DAC), Las Vegas, United States of America (the). IEEE. Peer-reviewed.
  DOI: 10.1145/3316781.3317787
• Prabakaran, B. S., Rehman, S., Shafique, M. (2019). XBioSiP. In Proceedings of the 56th Annual Design Automation Conference 2019. 2019 56th ACM/IEEE Design Automation Conference (DAC), Las Vegas, United States of America (the). IEEE. Peer-reviewed.
  DOI: 10.1145/3316781.3317933
• Kuznets, R., Prosperi, L., Schmid, U., Fruzsa, K. (2019). Causality and Epistemic Reasoning in Byzantine Multi-Agent Systems. In L. Moss (Ed.), Electronic Proceedings in Theoretical Computer Science (pp. 293–312). Electronic Proceedings in Theoretical Computer Science. Peer-reviewed.
  DOI: 10.4204/eptcs.297.19
• Marchisio, A., Hanif, M. A., Khalid, F., Plastiras, G., Kyrkou, C., Theocharides, T., Shafique, M. (2019). Deep Learning for Edge Computing: Current Trends, Cross-Layer Optimizations, and Open Research Challenges. In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Miami, United States of America (the). IEEE. Peer-reviewed.
  DOI: 10.1109/isvlsi.2019.00105
• Kriebel, F., Rehman, S., Shafique, M. (2019). Studying Aging and Soft Error Mitigation Jointly under Constrained Scenarios in Multi-Cores. In 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS). 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes, Greece. IEEE. Peer-reviewed.
  DOI: 10.1109/iolts.2019.8854444
• Rathore, V., Chaturvedi, V., Singh, A. K., Srikanthan, T., Shafique, M. (2019). Towards Scalable Lifetime Reliability Management for Dark Silicon Manycore Systems. In 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS). 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes, Greece. IEEE. Peer-reviewed.
  DOI: 10.1109/iolts.2019.8854454
• Khalid, F., Ali, H., Tariq, H., Hanif, M. A., Rehman, S., Ahmed, R., Shafique, M. (2019). QuSecNets: Quantization-based Defense Mechanism for Securing Deep Neural Network against Adversarial Attacks. In 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS). 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes, Greece. IEEE. Peer-reviewed.
  DOI: 10.1109/iolts.2019.8854377
• Nowak, T., Schmid, U., Winkler, K. (2019). Topological Characterization of Consensus under General Message Adversaries. In Proceedings of the 2019 ACM Symposium on Principles of Distributed Computing. 38th ACM Symposium on Principles of Distributed Computing (PODC’19), Toronto, Canada. ACM. Peer-reviewed.
  DOI: 10.1145/3293611.3331624
• Winkler, K., Schmid, U., Moses, Y. (2019). A Characterization of Consensus Solvability for Closed Message Adversaries. In P. Felber, R. Friedman, S. Gilbert, A. Miller (Eds.), 23rd International Conference on Principles of Distributed Systems (pp. 17:1-17:16). Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik. Peer-reviewed.
  DOI: 10.4230/LIPIcs.OPODIS.2019.17
• Khalid, F., Hanif, M. A., Rehman, S., Ahmed, R., Shafique, M. (2019). TrISec: Training Data-Unaware Imperceptible Security Attacks on Deep Neural Networks. In 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS). 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes, Greece. IEEE. Peer-reviewed.
  DOI: 10.1109/iolts.2019.8854425
• Hanif, M. A., Zuhaib Akbar, M., Ahmed, R., Rehman, S., Jantsch, A., Shafique, M. (2019). MemGANs: Memory Management for Energy-Efficient Acceleration of Complex Computations in Hardware Architectures for Generative Adversarial Networks. In 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED). 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Lausanne, Switzerland. IEEE. Peer-reviewed.
  DOI: 10.1109/islped.2019.8824833
• Paverd, A., Völp, M., Brasser, F., Schunter, M., Asokan, N., Sadeghi, A.-R., Esteves-Verissimo, P., Steininger, A., Holz, T. (2019). Sustainable Security Safety: Challenges and Opportunities. In M. Asplund M. Paulitsch (Eds.), Proceedings 4th International Workshop on Security and Dependability of Critical Embedded Real-Time Systems (CERTS 2019) (p. 13). Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik. Peer-reviewed.
  DOI: 10.4230/OASIcs.CERTS.2019.4 / Project: Intel CARS
• Mrazek, V., Vasicek, Z., Sekanina, L., Hanif, M. A., Shafique, M. (2019). ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. In Proceeding of 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD’19) (pp. 1–8). IEEE. Peer-reviewed.
  HDL: 20.500.12708/58006
• Hussain, S., Shafique, M., Henkel, J. (2019). A Fine-Grained Soft Error Resilient Architecture under Power Considerations. In 2019 Design, Automation Test in Europe Conference Exhibition (DATE). 2019 IEEE/ACM Design, Automation and Test in Europe Conference (DATE’19), Florence, Italy. IEEE. Peer-reviewed.
  DOI: 10.23919/date.2019.8714797
• Hussain, S., Shafique, M., Henkel, J. (2019). Thermal-Awareness in a Soft Error Tolerant Architecture. In 2019 Design, Automation Test in Europe Conference Exhibition (DATE). 2019 IEEE/ACM Design, Automation and Test in Europe Conference (DATE’19), Florence, Italy. IEEE. Peer-reviewed.
  DOI: 10.23919/date.2019.8715105
• Abbassi, I. H., Khalid, F., Rehman, S., Kamboh, A. M., Jantsch, A., Garg, S., Shafique, M. (2019). TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint. In 2019 Design, Automation Test in Europe Conference Exhibition (DATE). 2019 IEEE/ACM Design, Automation and Test in Europe Conference (DATE’19), Florence, Italy. IEEE. Peer-reviewed.
  DOI: 10.23919/date.2019.8714829
• Brandalero, M., Shafique, M., Carro, L., Beck, A. C. S. (2019). TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable Acceleration. In 2019 Design, Automation Test in Europe Conference Exhibition (DATE). 2019 IEEE/ACM Design, Automation and Test in Europe Conference (DATE’19), Florence, Italy. IEEE. Peer-reviewed.
  DOI: 10.23919/date.2019.8715121
• Marchisio, A., Hanif, M. A., Shafique, M. (2019). CapsAcc: An Efficient Hardware Accelerator for CapsuleNets with Data Reuse. In 2019 Design, Automation Test in Europe Conference Exhibition (DATE). 2019 IEEE/ACM Design, Automation and Test in Europe Conference (DATE’19), Florence, Italy. IEEE. Peer-reviewed.
  DOI: 10.23919/date.2019.8714922
• Khalid, F., Hanif, M. A., Rehman, S., Qadir, J., Shafique, M. (2019). FAdeML: Understanding the Impact of Pre-Processing Noise Filtering on Adversarial Machine Learning. In 2019 Design, Automation Test in Europe Conference Exhibition (DATE). 2019 IEEE/ACM Design, Automation and Test in Europe Conference (DATE’19), Florence, Italy. IEEE. Peer-reviewed.
  DOI: 10.23919/date.2019.8715141
• Marchisio, A., Nanfa, G., Khalid, F., Hanif, M. A., Martina, M., Shafique, M. (2019). CapsAttacks: Robust and Imperceptible Adversarial Attacks on Capsule Networks. In Proceedings of Workshop on Uncertainty and Robustness in Deep Learning (UDL) 2019 at ICML’19 (pp. 1–9). Peer-reviewed.
  HDL: 20.500.12708/58025
• Steininger, A., Schwendinger, M. (2019). A Systematic Approach to Clock Failure Detection. In 2019 Austrochip Workshop on Microelectronics (Austrochip). Austrochip Workshop on Microelectronics, Wien, Austria. Peer-reviewed.
  DOI: 10.1109/austrochip.2019.00018 / Project: Intel CARS

2018

• Pudukotai Dinakarrao, S. M., Jantsch, A., Shafique, M. (2018). SmartDPM: Machine Learning-based Dynamic Power Management for Multi-Core Microprocessors. Journal of Low Power Electronics and Applications, 14(4), 460–474. Peer-reviewed.
  DOI: 10.1166/jolpe.2018.1576
• Polzer, T., Huemer, F., Steininger, A. (2018). Refined Metastability Characterization Using a Time-to-Digital Converter. Microelectronics Reliability, 80, 91–99. Peer-reviewed.
  DOI: 10.1016/j.microrel.2017.11.017
• Biely, M., Robinson, P., Schmid, U., Schwarz, M., Winkler, K. (2018). Gracefully degrading consensus and k-set agreement in directed dynamic networks. Theoretical Computer Science, 726, 41–77. Peer-reviewed.
  DOI: 10.1016/j.tcs.2018.02.019
• Zhu, D., Shafique, M., Lin, M., Pasricha, S. (2018). Guest Editorial: Special Issue on Low-Power Dependable Computing. IEEE Transactions on Sustainable Computing, 3(3), 137–138.
  DOI: 10.1109/tsusc.2018.2813078
• Abbassi, I. H., Khalid, F., Hasan, O., Kamboh, A. M., Shafique, M. (2018). McSeVIC: A Model Checking Based Framework for Security Vulnerability Analysis of Integrated Circuits. IEEE Access, 6, 32240–32257. Peer-reviewed.
  DOI: 10.1109/access.2018.2846583
• Lee, H., Shafique, M., Al Faruque, M. A. (2018). Aging-Aware Workload Management on Embedded GPU Under Process Variation. IEEE Transactions on Computers, 67(7), 920–933. Peer-reviewed.
  DOI: 10.1109/tc.2018.2789904
• Mazahir, S., Hasan, O., Shafique, M. (2018). Adaptive Approximate Computing in Arithmetic Datapaths. IEEE Design and Test, 35(4), 65–74. Peer-reviewed.
  DOI: 10.1109/mdat.2017.2772874
• Kanduri, A., Haghbayan, M.-H., Rahmani, A. M., Shafique, M., Jantsch, A., Liljeberg, P. (2018). adBoost: Thermal Aware Performance Boosting Through Dark Silicon Patterning. IEEE Transactions on Computers, 67(8), 1062–1077. Peer-reviewed.
  DOI: 10.1109/tc.2018.2805683
• Gillani, G. A., Hanif, M. A., Krone, M., Gerez, S. H., Shafique, M., Kokkeler, A. B. J. (2018). SquASH: Approximate Square-Accumulate with Self-Healing. IEEE Access, 6, 49112–49128. Peer-reviewed.
  DOI: 10.1109/access.2018.2868036
• Sampaio, F. M., Zatt, B., Shafique, M., Henkel, J., Bampi, S. (2018). Hybrid Scratchpad Video Memory Architecture for Energy-Efficient Parallel HEVC. IEEE Transactions on Circuits and Systems for Video Technology, 29(10), 3046–3060. Peer-reviewed.
  DOI: 10.1109/tcsvt.2018.2870825
• Salehi, M., Ejlali, A., Shafique, M. (2018). Run-Time Adaptive Power-Aware Reliability Management for Manycores. IEEE Design and Test, 35(5), 36–44. Peer-reviewed.
  DOI: 10.1109/mdat.2017.2775738
• Akbari, O., Kamal, M., Afzali-Kusha, A., Pedram, M., Shafique, M. (2018). Towards Approximate Computing for Coarse-Grained Reconfigurable Architectures. IEEE Micro, 38(6), 63–72. Peer-reviewed.
  DOI: 10.1109/mm.2018.2873951
• Hanif, M. A., Marchisio, A., Arif, T., Hafiz, R., Rehman, S., Shafique, M. (2018). X-DNNs: Systematic Cross-Layer Approximations for Energy-Efficient Deep Neural Networks. Journal of Low Power Electronics, 14(4), 520–534. Peer-reviewed.
  DOI: 10.1166/jolpe.2018.1575
• Chatterjee, K., Pavlogiannis, A., Kößler, A., Schmid, U. (2018). Automated Competitive Analysis of Real-time Scheduling with Graph Games. Real-Time Systems, 54(1), 166–207. Peer-reviewed.
  DOI: 10.1007/s11241-017-9293-4
• Iqbal, S., Sardar, M. U., Khalid, F., Hasan, O. (2018). Statistical Model Checking of Relief Supply Location and Distribution in Natural Disaster Management. International Journal of Disaster Risk Reduction, 31, 1043–1053. Peer-reviewed.
  DOI: 10.1016/j.ijdrr.2018.04.010
• Khalid, F., Hasan, S. R., Hasan, O., Awwad, F. (2018). Runtime Hardware Trojan Monitors Through Modeling Burst Mode Communication Using Formal Verification. Integration, 61, 62–76. Peer-reviewed.
  DOI: 10.1016/j.vlsi.2017.11.003
• Schmid, U., Widder, J. (Eds.). (2018). 32nd International Symposium on Distributed Computing. Dagstuhl Publishing LIPICS. Peer-reviewed.
  DOI: 10.4230/LIPIcs.DISC.2018.0
• Pagani, S., Chen, J.-J., Shafique, M., Henkel, J. (2018). Advanced Techniques for Power, Energy, and Thermal Management for Clustered Manycores. Springer International Publishing.
  DOI: 10.1007/978-3-319-77479-4
• Khdr, H., Pagani, S., Shafique, M., Henkel, J. (2018). Dark Silicon Aware Resource Management for Many-Core Systems. In Advances in Computers (pp. 127–170). Elsevier.
  DOI: 10.1016/bs.adcom.2018.03.002
• Perner, M., Schmid, U. (2018). Self-Stabilizing High-Speed Communication in Multi-Synchronous GALS Architectures (TUW-268547).
  HDL: 20.500.12708/39426
• Schwarz, M., Schmid, U. (2018). On the Strongest Message Adversary for Consensus in Directed Dynamic Networks (TUW-269285).
  HDL: 20.500.12708/39450
• Pfleger, D., Schmid, U. (2018). On Knowledge and Communication Complexity in Distributed Systems (TUW-269752).
  HDL: 20.500.12708/39457
• Schmid, U. (2018). FWF-Proposal DMAC: Digital Modeling of Asynchronous Integrated Circuits (TUW-278607).
  HDL: 20.500.12708/39717
• Öhlinger, D. (2018). Involution Tool (TUW-278633).
  HDL: 20.500.12708/39720
• Függer, M., Maier, J., Najvirt, R., Nowak, T., Schmid, U. (2018). A Faithful Binary Circuit Model with Adversarial Noise. In 2018 Design, Automation Test in Europe Conference Exhibition (DATE). 2018 Design, Automation Test in Europe Conference Exhibition, Dresden, Germany. IEEE.
  DOI: 10.23919/DATE.2018.8342219 / Download: PDF
• Schmid, U., Schwarz, M., Winkler, K. (2018). On the Strongest Message Adversary for Consensus in Directed Dynamic Networks. In Structural Information and Communication Complexity (pp. 102–120). Springer International Publishing. Peer-reviewed.
  DOI: 10.1007/978-3-030-01325-7_13
• Pfleger, D., Schmid, U. (2018). On Knowledge and Communication Complexity in Distributed Systems. In Structural Information and Communication Complexity (pp. 312–330). Springer International Publishing. Peer-reviewed.
  DOI: 10.1007/978-3-030-01325-7_27
• Hailesellasie, M., Hasan, S. R., Khalid, F., Wad, F. A., Shafique, M. (2018). FPGA-Based Convolutional Neural Network Architecture with Reduced Parameter Requirements. In 2018 IEEE International Symposium on Circuits and Systems (ISCAS). 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florenz, Italy. Peer-reviewed.
  DOI: 10.1109/iscas.2018.8351283
• Khalid, F., Hanif, M. A., Rehman, S., Shafique, M. (2018). Security for Machine Learning-based Systems: Attacks and Challenges during Training and Inference. In 16th International Conference on Frontiers of Information Technology (FIT) (pp. 1–6).
  HDL: 20.500.12708/55714
• Afek, Y., Keidar, I., Patt-Shamir, B., Rajsbaum, S., Schmid, U., Taubenfeld, G. (2018). 2018 Edsger W. Dijkstra Prize in Distributed Computing. In Proceedings of the 2018 ACM Symposium on Principles of Distributed Computing. ACM Press.
  DOI: 10.1145/3212734.3232540
• Perner, M., Schmid, U. (2018). Self-Stabilizing High-Speed Communication in Multi-Synchronous GALS Architectures. In 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). 24th IEEE International Symposium on On-Line Testing And Robust System Design (IOLTS’18), Platja D’Aro, Spain. Peer-reviewed.
  DOI: 10.1109/iolts.2018.8474221
• Kuznets, R., Lellmann, B. (2018). Interpolation for Intermediate Logics via Hyper- and Linear Nested Sequents. In G. Bezhanishvili, G. D´Agostino, G. Metcalfe, T. Studer (Eds.), Advances in Modal Logic, Volume 12 (pp. 473–492). College Publications. Peer-reviewed.
  HDL: 20.500.12708/57374
• Bader, M., Todoran, G., Beck, F., Binder, B., Buchegger, K. (2018). TransportBuddy: Navigation in Human Accessible Spaces. In C. Landschützer, M. Fritz, A. Wolfschluckner (Eds.), Proceedings of 7th Transport Research Arena TRA 2018 (p. 10). Zenodo. Peer-reviewed.
  DOI: 10.5281/zenodo.1486646
• Zeiner, M., Schwarz, M., Schmid, U. (2018). On linear-time data dissemination in dynamic trees. In CSASC 2018 - Book of Abstracts (p. 113).
  HDL: 20.500.12708/57537
• Fan, C., Meng, Y., Maier, J., Bartocci, E., Mitra, S., Schmid, U. (2018). Verifying nonlinear analog and mixed-signal circuits with inputs. In IFAC-PapersOnLine (pp. 241–246). IFAC-PapersOnLine. Peer-reviewed.
  DOI: 10.1016/j.ifacol.2018.08.041
• Konnov, I., Widder, J. (2018). ByMC: Byzantine Model Checker. In T. Margaria B. Steffen (Eds.), Leveraging Applications of Formal Methods, Verification and Validation. Distributed Systems. ISoLA 2018, Proceedings, Part III (pp. 327–342). Springer. Peer-reviewed.
  DOI: 10.1007/978-3-030-03424-5_22
• Marchisio, A., Putra, R. V. W., Hanif, M. A., Shafique, M. (2018). HW/SW co-design and co-optimizations for deep learning. In Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications. Workshop on INTelligent Embedded Systems Architectures and Applications (INTESA), at the Embedded Systems Week (ESWeek), Turin, Italy. Peer-reviewed.
  DOI: 10.1145/3285017.3285022
• Shafique, M., Theocharides, T., Bouganis, C.-S., Hanif, M. A., Khalid, F., Hafiz, R., Rehman, S. (2018). An overview of next-generation architectures for machine learning: Roadmap, opportunities and challenges in the IoT era. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018 Design, Automation Test in Europe Conference Exhibition (DATE’18), Dresden, Germany. Peer-reviewed.
  DOI: 10.23919/date.2018.8342120
• Prabakaran, B. S., Rehman, S., Hanif, M. A., Ullah, S., Mazaheri, G., Kumar, A., Shafique, M. (2018). DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018 Design, Automation Test in Europe Conference Exhibition (DATE’18), Dresden, Germany. Peer-reviewed.
  DOI: 10.23919/date.2018.8342140
• Hanif, M. A., Hafiz, R., Shafique, M. (2018). Error resilience analysis for systematically employing approximate computing in convolutional neural networks. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018 Design, Automation Test in Europe Conference Exhibition (DATE’18), Dresden, Germany. Peer-reviewed.
  DOI: 10.23919/date.2018.8342139
• Castro-Godinez, J., Esser, S., Shafique, M., Pagani, S., Henkel, J. (2018). Compiler-driven error analysis for designing approximate accelerators. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018 Design, Automation Test in Europe Conference Exhibition (DATE’18), Dresden, Germany. Peer-reviewed.
  DOI: 10.23919/date.2018.8342163
• Akbari, O., Kamal, M., Afzali-Kusha, A., Pedram, M., Shafique, M. (2018). PX-CGRA: Polymorphic approximate coarse-grained reconfigurable architecture. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018 Design, Automation Test in Europe Conference Exhibition (DATE’18), Dresden, Germany. Peer-reviewed.
  DOI: 10.23919/date.2018.8342045
• Teimoori, M. T., Hanif, M. A., Ejlali, A., Shafique, M. (2018). AdAM: Adaptive approximation management for the non-volatile memory hierarchies. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018 Design, Automation Test in Europe Conference Exhibition (DATE’18), Dresden, Germany. Peer-reviewed.
  DOI: 10.23919/date.2018.8342113
• Rathore, V., Chaturvedi, V., Singh, A. K., Srikanthan, T., R., R., Lam, S.-K., Shafique, M. (2018). HiMap: A hierarchical mapping approach for enhancing lifetime reliability of dark silicon manycore systems. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018 Design, Automation Test in Europe Conference Exhibition (DATE’18), Dresden, Germany. Peer-reviewed.
  DOI: 10.23919/date.2018.8342153
• Rehman, S., Kriebel, F., Prabakaran, B. S., Khalid, F., Shafique, M. (2018). Hardware and Software Techniques for Heterogeneous Fault-Tolerance. In 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design (IOLTS), Platja d’Aro, Spain. Peer-reviewed.
  DOI: 10.1109/iolts.2018.8474219
• Khalid, F., Nanjiani, S., Hasan, S. R., Hasan, O., Awwad, F., Shafique, M. (2018). Low Power Digital Clock Multipliers for Battery-Operated Internet of Things (IoT) Devices. In 2018 IEEE International Symposium on Circuits and Systems (ISCAS). 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florenz, Italy. Peer-reviewed.
  DOI: 10.1109/iscas.2018.8351102
• Pathania, A., Khdr, H., Shafique, M., Mitra, T., Henkel, J. (2018). QoS-Aware Stochastic Power Management for Many-Cores. In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC). 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), San Fransisco, United States of America (the). Peer-reviewed.
  DOI: 10.1109/dac.2018.8465916
• Ullah, S., Rehman, S., Prabakaran, B. S., Kriebel, F., Hanif, M. A., Shafique, M., Kumar, A. (2018). Area-Optimized Low-Latency Approximate Multipliers for FPGA-based Hardware Accelerators. In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC). 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), San Fransisco, United States of America (the). Peer-reviewed.
  DOI: 10.1109/dac.2018.8465781
• Brandalero, M., S. Beck, A. C., Carro, L., Shafique, M. (2018). Approximate On-The-Fly Coarse-Grained Reconfigurable Acceleration for General-Purpose Applications. In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC). 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), San Fransisco, United States of America (the). Peer-reviewed.
  DOI: 10.1109/dac.2018.8465930
• Kriebel, F., Rehman, S., Hanif, M. A., Khalid, F., Shafique, M. (2018). Robustness for Smart Cyber Physical Systems and Internet-of-Things: From Adaptive Robustness Methods to Reliability and Security for Machine Learning. In 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong. Peer-reviewed.
  DOI: 10.1109/isvlsi.2018.00111
• Hanif, M. A., Khalid, F., Putra, R. V. W., Rehman, S., Shafique, M. (2018). Robust Machine Learning Systems: Reliability and Security for Deep Neural Networks. In 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). 24th IEEE International Symposium on On-Line Testing And Robust System Design (IOLTS’18), Platja D’Aro, Spain. Peer-reviewed.
  DOI: 10.1109/iolts.2018.8474192
• Marchisio, A., Hanif, M. A., Martina, M., Shafique, M. (2018). PruNet: Class-Blind Pruning Method For Deep Neural Networks. In 2018 International Joint Conference on Neural Networks (IJCNN). IEEE International Joint Conference on Neural Networks (IJCNN), Montréal, Canada. Peer-reviewed.
  DOI: 10.1109/ijcnn.2018.8489764
• Shafique, M., Khalid, F., Rehman, S. (2018). Intelligent Security Measures for Smart Cyber Physical Systems. In 2018 21st Euromicro Conference on Digital System Design (DSD). 2018 21st Euromicro Conference on Digital System Design (DSD), Prag, Czechia. Peer-reviewed.
  DOI: 10.1109/dsd.2018.00058
• Selvo, P., Masera, M., Peloso, R., Masera, G., Shafique, M., Martina, M. (2018). An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding. In The 6th Conference on Applications in Electronics Pervading Industry, Environment and Society (ApplePies) (pp. 1–6). Peer-reviewed.
  HDL: 20.500.12708/57604
• Venkataramani, V., Pathania, A., Shafique, M., Mitra, T., Henkel, J. (2018). Scalable Dynamic Task Scheduling on Adaptive Many-Core. In 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Hanoi, Viet Nam. Peer-reviewed.
  DOI: 10.1109/mcsoc2018.2018.00037
• Fuegger, M., Kinali, A., Lenzen, C., Wiederhake, B. (2018). Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance. In 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 24th IEEE International Symposium on Asynchronous Circuits and Systems, Wien, Austria. Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems. Peer-reviewed.
  DOI: 10.1109/async.2018.00025
• Függer, M., Nowak, T., Schwarz, M. (2018). Tight Bounds for Asymptotic and Approximate Consensus. In Proceedings of the 2018 ACM Symposium on Principles of Distributed Computing. 37th ACM Symposium on Principles of Distributed Computing (PODC’18), Egham, United Kingdom of Great Britain and Northern Ireland (the). ACM. Peer-reviewed.
  DOI: 10.1145/3212734.3212762
• Kukovec, J., Konnov, I., Widder, J. (2018). Reachability in Parameterized Systems: All Flavors of Threshold Automata. In S. Schewe L. Zhang (Eds.), 29th International Conference on Concurrency Theory (CONCUR 2018) (pp. 19:1-19:17). Schloss Dagstuhl - Leibniz-Zentrum für Informatik GmbH, Dagstuhl Publishing. Peer-reviewed.
  DOI: 10.4230/LIPIcs.CONCUR.2018.19
• Dragoi, C., Lazić, M., Widder, J. (2018). Communication-Closed Layers as Paradigm for Distributed Systems: A Manifesto. In Proceedings of the International Scientific Conference - Sinteza 2018. Sinteza 2018 International Scientific Conference on Information Technology and Data Related Research, Belgrad, Serbia. Singidunum University.
  DOI: 10.15308/sinteza-2018-131-138
• Huemer, F., Steininger, A. (2018). Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. In 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE CS Press, Austria. IEEE Xplore Digital Library. Peer-reviewed.
  DOI: 10.1109/async.2018.00014
• Huemer, F., Steininger, A. (2018). Advanced Delay-Insensitive 4-Phase Protocols. In 2018 Austrochip Workshop on Microelectronics (Austrochip). IEEE CS Press, Austria. IEEE Xplore Digital Library. Peer-reviewed.
  DOI: 10.1109/austrochip.2018.8520702
• Schütz, M., Steininger, A., Huemer, F., Lechner, J. (2018). State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. In 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE CS Press, Austria. IEEE Xplore Digital Library. Peer-reviewed.
  DOI: 10.1109/dft.2018.8602984 / Project: Intel CARS
• Huemer, F., Polzer, T., Steininger, A. (2018). Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. In 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE CS Press, Austria. IEEE Xplore Digital Library. Peer-reviewed.
  DOI: 10.1109/ddecs.2018.00032
• Mohammed, H., Howell, J., Hasan, S. R., Guo, N., Khalid, F., Elkeelany, O. (2018). Hardware Trojan Based Security Issues in Home Area Network: a Testbed Setup. In International Midwest Symposium on Circuits and Systems (pp. 1–4). IEEE.
  HDL: 20.500.12708/57754
• Javed, R. H., Siddique, A., Hafiz, R., Hasan, O., Shafique, M. (2018). ApproxCT: Approximate Clustering Techniques for Energy Efficient Computer Vision in Cyber-Physical Systems. In 2018 12th International Conference on Open Source Systems and Technologies (ICOSST). 2018 12th International Conference on Open Source Systems and Technologies (ICOSST), Lahore, Pakistan. IEEE. Peer-reviewed.
  DOI: 10.1109/icosst.2018.8632191
• Aminof, B., Rubin, S., Stoilkovska, I., Widder, J., Zuleger, F. (2018). Parameterized Model Checking of Synchronous Distributed Algorithms by Abstraction. In I. Dillig J. Palsberg (Eds.), Verification, Model Checking, and Abstract Interpretation : 19th International Conference, VMCAI 2018, Los Angeles, CA, USA, January 7-9, 2018, Proceedings. Cham. Peer-reviewed.
  DOI: 10.1007/978-3-319-73721-8_1 / Download: PDF

2017

• Steininger, A., Pawlak, A., Stopjakova, V. (2017). Foreword. Journal of Circuits, Systems, and Computers, 26(08), Article 1702001.
  DOI: 10.1142/s0218126617020017
• Pathania, A., Venkataramani, V., Shafique, M., Mitra, T., Henkel, J. (2017). Optimal Greedy Algorithm for Many-Core Scheduling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(6), 1054–1058. Peer-reviewed.
  DOI: 10.1109/tcad.2016.2618880
• Maier, J. (2017). Modeling the CMOS Inverter using Hybrid Systems. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:3-10163
  HDL: 20.500.12708/485 / Download: PDF / Project: SIC
• Konnov, I., Veith, H., Widder, J. (2017). On the completeness of bounded model checking for threshold-based distributed algorithms: Reachability. Information and Computation, 252, 95–109. Peer-reviewed.
  DOI: 10.1016/j.ic.2016.03.006
• Konnov, I., Lazić, M., Veith, H., Widder, J. (2017). Para^2: Parameterized Path Reduction, Acceleration, and SMT for Reachability in Threshold-Guarded Distributed Algorithms. Formal Methods in System Design, 51(2), 270–307. Invited and peer-reviewed.
  DOI: 10.1007/s10703-017-0297-4
• Savulimedu Veeravalli, V., Steininger, A., Schmid, U. (2017). A versatile architecture for long-term monitoring of single-event transient durations. Microprocessors and Microsystems, 53, 130–144. Peer-reviewed.
  DOI: 10.1016/j.micpro.2017.07.007
• Pagani, S., Khdr, H., Chen, J.-J., Shafique, M., Li, M., Henkel, J. (2017). Thermal Safe Power (TSP): Efficient Power Budgeting for Heterogeneous Manycore Systems in Dark Silicon. IEEE Transactions on Computers, 66(1), 147–162. Peer-reviewed.
  DOI: 10.1109/tc.2016.2564969
• Khdr, H., Pagani, S., Sousa, E., Lari, V., Pathania, A., Hannig, F., Shafique, M., Teich, J., Henkel, J. (2017). Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. IEEE Transactions on Computers, 66(3), 488–501. Peer-reviewed.
  DOI: 10.1109/tc.2016.2595560
• Mazahir, S., Hasan, O., Hafiz, R., Shafique, M., Henkel, J. (2017). Probabilistic Error Modeling for Approximate Adders. IEEE Transactions on Computers, 66(3), 515–530. Peer-reviewed.
  DOI: 10.1109/tc.2016.2605382
• Shafique, M., Rehman, S., Kriebel, F., Khan, M. U. K., Zatt, B., Subramaniyan, A., Vizzotto, B. B., Henkel, J. (2017). Application-Guided Power-Efficient Fault Tolerance for H.264 Context Adaptive Variable Length Coding. IEEE Transactions on Computers, 66(4), 560–574. Peer-reviewed.
  DOI: 10.1109/tc.2016.2616313
• Li, T., Shafique, M., Ambrose, J. A., Henkel, J., Parameswaran, S. (2017). Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors. IEEE Transactions on Computers, 66(4), 647–660. Peer-reviewed.
  DOI: 10.1109/tc.2016.2606378
• Pathania, A., Venkataramani, V., Shafique, M., Mitra, T., Henkel, J. (2017). Defragmentation of Tasks in Many-Core Architecture. ACM Transactions on Architecture and Code Optimization, 14(1), 1–21. Peer-reviewed.
  DOI: 10.1145/3050437
• Shafique, M., Garg, S. (2017). Computing in the Dark Silicon Era: Current Trends and Research Challenges. IEEE Design and Test, 34(2), 8–23. Peer-reviewed.
  DOI: 10.1109/mdat.2016.2633408
• Pagani, S., Pathania, A., Shafique, M., Chen, J.-J., Henkel, J. (2017). Energy Efficiency for Clustered Heterogeneous Multicores. IEEE Transactions on Parallel and Distributed Systems, 28(5), 1315–1330. Peer-reviewed.
  DOI: 10.1109/tpds.2016.2623616
• Mazahir, S., Hasan, O., Hafiz, R., Shafique, M. (2017). Probabilistic Error Analysis of Approximate Recursive Multipliers. IEEE Transactions on Computers, 66(11), 1982–1990. Peer-reviewed.
  DOI: 10.1109/tc.2017.2709542
• Qadir, J., Sathiaseelan, A., Farooq, U., Usama, M., Imran, M., Shafique, M. (2017). Approximate Networking for Universal Internet Access. Future Internet, 9(4), 94.
  DOI: 10.3390/fi9040094
• Shafique, M., Garg, S., Chandra, V. (2017). Guest Editors’ Introduction: Computing in the Dark Silicon Era. IEEE Design and Test, 34(2), 5–7.
  DOI: 10.1109/mdat.2017.2651065
• Polzer, T., Steininger, A. (2017). A Model for the Metastability Delay of Sequential Elements. Journal of Circuits, Systems, and Computers, 26(08), 1740010. Peer-reviewed.
  DOI: 10.1142/s0218126617400102
• Charron-Bost, B., Függer, M., Nowak, T. (2017). New transience bounds for max-plus linear systems. Discrete Applied Mathematics, 219, 83–99. Peer-reviewed.
  DOI: 10.1016/j.dam.2016.11.003
• Khan, M. U. K., Shafique, M., Henkel, J. (2017). Energy Efficient Embedded Video Processing Systems. Springer International Publishing.
  DOI: 10.1007/978-3-319-61455-7
• Bokhari, H., Shafique, M., Henkel, J., Parameswaran, S. (2017). Adroit Use of Dark Silicon for Power, Performance and Reliability Optimisation of NoCs. In The Dark Side of Silicon (pp. 291–325). Springer International Publishing. Peer-reviewed.
  DOI: 10.1007/978-3-319-31596-6_11
• Pagani, S., Khdr, H., Chen, J.-J., Shafique, M., Li, M., Henkel, J. (2017). Thermal Safe Power: Efficient Thermal-Aware Power Budgeting for Manycore Systems in Dark Silicon. In The Dark Side of Silicon (pp. 125–158). Springer International Publishing. Peer-reviewed.
  DOI: 10.1007/978-3-319-31596-6_5
• Pagani, S., Shafique, M., Henkel, J. (2017). Design Space Exploration and Run-Time Adaptation for Multicore Resource Management Under Performance and Power Constraints. In Handbook of Hardware/Software Codesign (pp. 301–332). Springer Science+Business Media. Peer-reviewed.
  DOI: 10.1007/978-94-017-7267-9_11
• Kuznets, R., Straßburger, L. (2017). Maehara-style Modal Nested Calculi (RR-9123).
  HDL: 20.500.12708/39305
• Ratasich, D., Höftberger, O., Isakovic, H., Shafique, M., Grosu, R. (2017). A Self-Healing Framework for Building Resilient Cyber-Physical Systems. In 2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC). 20th IEEE International Symposium on Real-Time Computing (ISORC 2017), Toronto, Canada. IEEE. Peer-reviewed.
  DOI: 10.1109/isorc.2017.7
• Fritz, B., Veeravalli, V. S., Steininger, A., Simek, V. (2017). Setup for an Experimental Study of Radiation Effects in 65nm CMOS. In 2017 Euromicro Conference on Digital System Design (DSD). 20th Euromicro Conference on Digital System Design, Wien, Austria. Peer-reviewed.
  DOI: 10.1109/dsd.2017.60
• Függer, M., Kinali, A., Lenzen, C., Polzer, T. (2017). Metastability-Aware Memory-Efficient Time-to-Digital Converters. In 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017), San Diego, California, United States of America (the). IEEE Computer Society.
  DOI: 10.1109/async.2017.12
• Függer, M., Nowak, T., Schwarz, M. (2017). Brief Announcement: Lower Bounds for Asymptotic Consensus in Dynamic Networks. In A. W. Richa (Ed.), 31st International Symposium on Distributed Computing (DISC 2017) (p. 3). Schloss Dagstuhl – Leibniz-Zentrum für Informatik.
  DOI: 10.4230/LIPIcs.DISC.2017.51
• Tarawneh, G., Függer, M., Lenzen, C. (2017). Metastability Tolerant Computing. In 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017), San Diego, California, United States of America (the). IEEE Computer Society.
  DOI: 10.1109/async.2017.9
• Konnov, I., Lazić, M., Veith, H., Widder, J. (2017). A short counterexample property for safety and liveness verification of fault-tolerant distributed algorithms. In Proceedings of the 44th ACM SIGPLAN Symposium on Principles of Programming Languages. 44th ACM SIGPLAN Symposium on Principles of Programming Languages (POPL), Paris, France. ACM. Peer-reviewed.
  DOI: 10.1145/3009837.3009860
• Najvirt, R., Polzer, T., Steininger, A. (2017). Measuring Metastability with Free-Running Clocks. In 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017), San Diego, California, United States of America (the). IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/async.2017.18
• Polzer, T., Huemer, F., Steininger, A. (2017). Measuring metastability using a time-to-digital converter. In 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Dresden, Germany. IEEE Service Center. Peer-reviewed.
  DOI: 10.1109/ddecs.2017.7934582
• Lazić, M., Konnov, I., Widder, J., Bloem, R. (2017). Synthesis of Distributed Algorithms with Parameterized Threshold Guards. In J. Aspnes, A. Bessani, P. Felber, J. Leitao (Eds.), 21st International Conference on Principles of Distributed Systems (OPODIS 2017) (pp. 32:1-32:20). LIPIcs-Leibniz International Proceedings in Informatics. Peer-reviewed.
  DOI: 10.4230/LIPIcs.OPODIS.2017.32
• Zeiner, M., Schmid, U., Schwarz, M. (2017). On Linear-Time Data Dissemination in Dynamic Rooted Trees. In 19th ÖMG Congress and Annual DMV Meetig Program and Books of Abstracts (p. 87).
  HDL: 20.500.12708/57124
• Chattopadhyay, A., Prakash, A., Shafique, M. (2017). Secure Cyber-Physical Systems: Current trends, tools and open research problems. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. 2017 IEEE/ACM 20th Design, Automation and Test in Europe Conference (DATE’17), Lausanne, Switzerland. IEEE. Peer-reviewed.
  DOI: 10.23919/date.2017.7927154
• Bukhari, S. A. A., Lodhi, F. K., Hasan, O., Shafique, M., Henkel, J. (2017). CAnDy-TM: Comparative analysis of dynamic thermal management in many-cores using model checking. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. 2017 IEEE/ACM 20th Design, Automation and Test in Europe Conference (DATE’17), Lausanne, Switzerland. IEEE. Peer-reviewed.
  DOI: 10.23919/date.2017.7927191
• Pathania, A., Khdr, H., Shafique, M., Mitra, T., Henkel, J. (2017). Scalable probabilistic power budgeting for many-cores. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. 2017 IEEE/ACM 20th Design, Automation and Test in Europe Conference (DATE’17), Lausanne, Switzerland. IEEE. Peer-reviewed.
  DOI: 10.23919/date.2017.7927108
• Subramaniyan, A., Rehman, S., Shafique, M., Kumar, A., Henkel, J. (2017). Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. 2017 IEEE/ACM 20th Design, Automation and Test in Europe Conference (DATE’17), Lausanne, Switzerland. IEEE. Peer-reviewed.
  DOI: 10.23919/date.2017.7926955
• El-Harouni, W., Rehman, S., Prabakaran, B. S., Kumar, A., Hafiz, R., Shafique, M. (2017). Embracing approximate computing for energy-efficient motion estimation in high efficiency video coding. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. 2017 IEEE/ACM 20th Design, Automation and Test in Europe Conference (DATE’17), Lausanne, Switzerland. IEEE. Peer-reviewed.
  DOI: 10.23919/date.2017.7927209
• Ayub, M. K., Hasan, O., Shafique, M. (2017). Statistical Error Analysis for Low Power Approximate Adders. In Proceedings of the 54th Annual Design Automation Conference 2017. 2017 ACM/EDAC/IEEE 54th Design Automation Conference (DAC’17), Austin, Texas, United States of America (the). ACM. Peer-reviewed.
  DOI: 10.1145/3061639.3062319
• Hanif, M. A., Hafiz, R., Hasan, O., Shafique, M. (2017). QuAd. In Proceedings of the 54th Annual Design Automation Conference 2017. 2017 ACM/EDAC/IEEE 54th Design Automation Conference (DAC’17), Austin, Texas, United States of America (the). ACM. Peer-reviewed.
  DOI: 10.1145/3061639.3062306
• Lee, H., Shafique, M., Al Faruque, M. A. (2017). Low-overhead Aging-aware Resource Management on Embedded GPUs. In Proceedings of the 54th Annual Design Automation Conference 2017. 2017 ACM/EDAC/IEEE 54th Design Automation Conference (DAC’17), Austin, Texas, United States of America (the). ACM. Peer-reviewed.
  DOI: 10.1145/3061639.3062277
• Shafique, M., Hafiz, R., Javed, M. U., Abbas, S., Sekanina, L., Vasicek, Z., Mrazek, V. (2017). Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. In 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI’17), Bochum, Germany. IEEE. Peer-reviewed.
  DOI: 10.1109/isvlsi.2017.124
• Andjelkovic, M., Krstic, M., Kraemer, R., Veeravalli, V. S., Steininger, A. (2017). A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. In Proceedings of the 26th IEEE Asian Test Symposium (ATS´17) (pp. 1–6). Peer-reviewed.
  HDL: 20.500.12708/57265
• Konnov, I., Widder, J., Spegni, F., Spalazzi, L. (2017). Accuracy of Message Counting Abstraction in Fault-Tolerant Distributed Algorithms. In A. Bouajjani D. Monniaux (Eds.), Verification, Model Checking, and Abstract Interpretation : 18th International Conference, VMCAI 2017, Paris, France, January 15–17, 2017, Proceedings. Springer Heidelberg.
  DOI: 10.1007/978-3-319-52234-0_19 / Download: PDF

2016

• Függer, M., Nowak, T., Schmid, U. (2016). Unfaithful Glitch Propagation in Existing Binary Circuit Models. IEEE Transactions on Computers, 65(3), 964–978. Peer-reviewed.
  DOI: 10.1109/tc.2015.2435791
• Shafique, M., Ivanov, A., Vogel, B., Henkel, J. (2016). Scalable Power Management for On-Chip Systems with Malleable Applications. IEEE Transactions on Computers, 65(11), 3398–3412. Peer-reviewed.
  DOI: 10.1109/tc.2016.2540631
• Dolev, D., Függer, M., Lenzen, C., Perner, M., Schmid, U. (2016). HEX: Scaling Honeycombs is Easier than Scaling Clock Trees. Journal of Computer and System Sciences, 82(5), 929–956. Peer-reviewed.
  DOI: 10.1016/j.jcss.2016.03.001
• Bloem, R., Jacobs, S., Khalimov, A., Konnov, I., Rubin, S., Veith, H., Widder, J. (2016). Decidability of Parameterized Verification. ACM SIGACT News, 47(2), 53–64.
  DOI: 10.1145/2951860.2951873
• Shafique, M., Khan, M. U. K., Henkel, J. (2016). Content-Aware Low-Power Configurable Aging Mitigation for SRAM Memories. IEEE Transactions on Computers, 65(12), 3617–3630. Peer-reviewed.
  DOI: 10.1109/tc.2016.2553025
• Chen, K.-H., Chen, J.-J., Kriebel, F., Rehman, S., Shafique, M., Henkel, J. (2016). Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity. IEEE Transactions on Computers, 65(11), 3441–3455. Peer-reviewed.
  DOI: 10.1109/tc.2016.2532862
• Steininger, A. (2016). Fifty Shades of Synchrony. In A. Mokhov (Ed.), This Asynchronous Woirld (pp. 294–300). Newcastle University.
  HDL: 20.500.12708/29323
• Zeiner, M., Schmid, U., Schilcher, U., Bettstetter, C. (2016). FWF-Proposal SPRG: Structural Properties of Random Graphs.
  HDL: 20.500.12708/39096
• Biely, M., Robinson, P., Schmid, U., Schwarz, M., Winkler, K. (2016). Gracefully Degrading Consensus and k-Set Agreement in Directed Dynamic Networks (TUW-258404).
  HDL: 20.500.12708/39151
• Steininger, A., Maier, J., Najvirt, R. (2016). The Metastable Behavior of a Schmitt-Trigger. In 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), Porto Alegre, Brazil. IEEE.
  DOI: 10.1109/ASYNC.2016.19 / Download: PDF
• Steininger, A., Najvirt, R., Maier, J. (2016). Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? In 2016 Euromicro Conference on Digital System Design (DSD). 2016 Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus. IEEE.
  DOI: 10.1109/DSD.2016.56 / Download: PDF
• Schwarz, M., Winkler, K., Schmid, U. (2016). Fast consensus under eventually stabilizing message adversaries. In Proceedings of the 17th International Conference on Distributed Computing and Networking. 17th International Conference on Distributed Computing and Networking, Singapore, Singapore. ACM. Peer-reviewed.
  DOI: 10.1145/2833312.2833323
• Charron-Bost, B., Függer, M., Nowak, T. (2016). Fast, Robust, Quantizable Approximate Consensus. In I. Chatzigiannakis, M. Mitzenmacher, Y. Rabani, D. Sangiorgi (Eds.), Proceedings 43rd International Colloquium on Automata, Languages, and Programming (ICALP’16) (pp. 137:1-137:14). Leibniz International Proceedings in Informatics (LIPIcs). Peer-reviewed.
  DOI: 10.4230/LIPIcs.ICALP.2016.137
• Pfleger, D., Schmid, U. (2016). A Framework for Connectivity Monitoring in Wireless Sensor Networks. In Proceedings 10th International Conference on Sensor Technlogies and Applications (SENSORCOMM’16) (pp. 40–48). IARIA XPS Press. Peer-reviewed.
  HDL: 20.500.12708/56746
• Rehman, S., El-Harouni, W., Shafique, M., Kumar, A., Henkel, J. (2016). Architectural-space exploration of approximate multipliers. In Proceedings of the 35th International Conference on Computer-Aided Design. The IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, United States of America (the). ACM New York, NY, USA. Peer-reviewed.
  DOI: 10.1145/2966986.2967005
• Bogdan, P., Pande, P. P., Amrouch, H., Shafique, M., Henkel, J. (2016). Power and Thermal Management in Massive Multicore Chips: Theoretical Foundation meets Architectural Innovation and Resource Allocation. In CASES (pp. 1–2). ACM.
  DOI: 10.1145/2968455.2974013
• Huemer, F., Lechner, J., Steininger, A. (2016). A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes. In Proceedings 2016 IEEE International Conference on Computer Design (pp. 392–395). Peer-reviewed.
  HDL: 20.500.12708/56881
• Polzer, T., Huemer, F., Steininger, A. (2016). A Programmable Delay Line for Metastability Characterization in FPGAs. In Proceedings 24th Austrian Workshop on Microelectronics (p. 6). Peer-reviewed.
  HDL: 20.500.12708/56883
• Veeravalli, V. S., Steininger, A. (2016). Design and Physical Implementation of a Target ASIC for SET Experiments. In Proc. 2016 Euromicro Conference on Digital System Design (DSD) (pp. 694–697). IEEE. Peer-reviewed.
  HDL: 20.500.12708/56884 / Project: EASET
• Veeravalli, V. S., Steininger, A. (2016). Study of a Delayed Single-Event Effect in the Muller C-element. In Proc 21st IEEE European Test Symposium. 21st IEEE European Test Symposium, Amsterdam, Netherlands (the). Peer-reviewed.
  HDL: 20.500.12708/56885 / Project: EASET
• Polzer, T., Steininger, A. (2016). A General Approach for Comparing Metastable Behavior of Digital CMOS Gates. In Proc 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (p. 6). Peer-reviewed.
  HDL: 20.500.12708/56886
• Kinali, A., Huemer, F., Lenzen, C. (2016). Fault-Tolerant Clock Synchronization with High Precision. In 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2016 IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, United States of America (the). Peer-reviewed.
  DOI: 10.1109/isvlsi.2016.88
• Konnov, I., Veith, H., Widder, J. (2016). What You Always Wanted to Know About Model Checking of Fault-Tolerant Distributed Algorithms. In Perspectives of System Informatics : 10th International Andrei Ershov Informatics Conference, PSI 2015, in Memory of Helmut Veith, Kazan and Innopolis, Russia, August 24-27, 2015, Revised Selected Papers (pp. 6–21). Springer.
  DOI: 10.1007/978-3-319-41579-6_2 / Download: PDF

2015

• Függer, M., Kößler, A., Nowak, T., Schmid, U., Zeiner, M. (2015). The effect of forgetting on the performance of a synchronizer. Performance Evaluation, 93, 1–16. Peer-reviewed.
  DOI: 10.1016/j.peva.2015.08.002
• Steininger, A., Zimmermann, H., Jantsch, A., Hofbauer, M., Schmid, U., Schweiger, K., Savulimedu Veeravalli, V. (2015). Building reliable systems-on-chip in nanoscale technologies. Elektrotechnik Und Informationstechnik : E i, 132(6), 301–306. Peer-reviewed.
  DOI: 10.1007/s00502-015-0319-0
• Charron-Bost, B., Függer, M., Welch, J. L., Widder, J. (2015). Time Complexity of Link Reversal Routing. ACM Transactions on Algorithms, 11(3), 1–39. Peer-reviewed.
  DOI: 10.1145/2644815
• Dolev, D., Függer, M., Lenzen, C., Schmid, U., Steininger, A. (2015). Fault-tolerant Distributed Systems in Hardware. Bulletin of the EATCS, 2(116), 43.
  HDL: 20.500.12708/151760
• Polzer, T., Najvirt, R., Beck, F., Steininger, A. (2015). On the Appropriate Handling of Metastable Voltages in FPGAs. Journal of Circuits, Systems, and Computers, 25(03), 1640020. Peer-reviewed.
  DOI: 10.1142/s021812661640020x
• Resch, S., Steininger, A., Scherrer, C. (2015). A Composable Real-Time Architecture for Replicated Railway Applications. Journal of Systems Architecture, 61(9), 472–485. Peer-reviewed.
  DOI: 10.1016/j.sysarc.2015.04.003
• Bloem, R., Jacobs, S., Khalimov, A., Konnov, I., Rubin, S., Veith, H., Widder, J. (2015). Decidability of Parameterized Verification. In Synthesis Lectures on Distributed Computing Theory (p. 170). Morgan Claypool Publishers.
  DOI: 10.2200/s00658ed1v01y201508dct013
• Schwarz, M., Winkler, K., Schmid, U. (2015). Fast Consensus under Eventually Stabilizing Message Adversaries (TUW-240061).
  HDL: 20.500.12708/38462
• Pfleger, D., Schmid, U. (2015). A Framework for Connectivity Monitoring in Wireless Sensor Networks (TUW-241107).
  HDL: 20.500.12708/38487
• Najvirt, R., Függer, M., Nowak, T., Schmid, U., Hofbauer, M., Schweiger, K. (2015). Experimental Validation of a Faithful Binary Circuit Model. In Proceedings of the 25th edition on Great Lakes Symposium on VLSI. Great Lakes Symposium on VLSI (GLSVLSI’15), Pittsburgh, United States of America (the). Peer-reviewed.
  DOI: 10.1145/2742060.2742081
• Konnov, I., Veith, H., Widder, J. (2015). SMT and POR Beat Counter Abstraction: Parameterized Model Checking of Threshold-Based Distributed Algorithms. In Computer Aided Verification (pp. 85–102). LNCS Springer. Peer-reviewed.
  DOI: 10.1007/978-3-319-21690-4_6
• Biely, M., Robinson, P., Schmid, U., Schwarz, M., Winkler, K. (2015). Gracefully Degrading Consensus and k-Set Agreement in Directed Dynamic Networks. In Networked Systems Third International Conference, NETYS 2015, Agadir, Morocco, May 13-15, 2015, Revised Selected Papers. The international Conference on NETworked sYStems, Agadir, Morocco. Springer LNCS. Peer-reviewed.
  DOI: 10.1007/978-3-319-26850-7_8
• Függer, M., Najvirt, R., Nowak, T., Schmid, U. (2015). Towards binary circuit models that faithfully capture physical solvability. In Proceedings of the 2015 Design, Automation Test in Europe Conference Exhibition (DATE’15) (pp. 1455–1460). Peer-reviewed.
  HDL: 20.500.12708/56310
• Najvirt, R., Steininger, A. (2015). How to Synchronize a Pausible Clock to a Reference. In 21st IEEE International Symposium on Asynchronous Circuits and Systems (p. 8). Peer-reviewed.
  HDL: 20.500.12708/56348
• Schütz, M., Huemer, F., Steininger, A. (2015). A Practical Comparison of 2-Phase Delay Insensitve Communication Protocols. In Austrochip Workshop on Microelectronics (p. 6). Peer-reviewed.
  HDL: 20.500.12708/56349
• Huemer, F., Schütz, M., Steininger, A. (2015). Revisiting Sorting Network based Completion Detection for 4 Phase Delay Insensitive Codes. In Austrochip Workshop on Microelectronics (p. 6). Peer-reviewed.
  HDL: 20.500.12708/56350
• Najvirt, R., Polzer, T., Beck, F., Steininger, A. (2015). Containment of Metastable Voltages in FPGAs. In 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (p. 6). Peer-reviewed.
  HDL: 20.500.12708/56351
• Polzer, T., Steininger, A. (2015). Measuring the Distribution of Metastable Upsets over Time. In Measuring the Distribution of Metastable Upsets over Time (p. 8). Peer-reviewed.
  HDL: 20.500.12708/56352
• Polzer, T., Steininger, A. (2015). Enhanced Metastability Characterization based on AC Analysis. In 18th Euromicro Conference on Digital System Design (p. 9). Peer-reviewed.
  HDL: 20.500.12708/56353
• Veeravalli, V. S., Steininger, A. (2015). Reliable and Continuous Measurement of SET Pulse Widths. In 18th Euromicro Conference on Digital System Design (p. 8). Peer-reviewed.
  HDL: 20.500.12708/56354
• Najvirt, R., Steininger, A. (2015). A Pausible Clock with Crystal Oscillator Accuracy. In 22nd European Conference on Circuit Theory and Design (p. 4). Peer-reviewed.
  HDL: 20.500.12708/56356
• Lechner, J., Steininger, A., Huemer, F. (2015). Methods for Analysing and Improving the Fault Resilience of Delay-Insensitive Codes. In 33rd IEEE International Conference on Computer Design (p. 8). Peer-reviewed.
  HDL: 20.500.12708/56358
• Veeravalli, V. S., Steininger, A. (2015). Can we trust SET Injection Models? In MEDIAN Finale Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (p. 6). Peer-reviewed.
  HDL: 20.500.12708/56359
• Najvirt, R., Steininger, A. (2015). A Versatile and Reliable Glitch Filter for Clocks. In 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (p. 8). Peer-reviewed.
  HDL: 20.500.12708/56360

2014

• Zeiner, M. (2014). On a family of $q$-binomial distributions. Mathematica Slovaca, 64(2), 479–510. Peer-reviewed.
  DOI: 10.2478/s12175-014-0220-z
• Dolev, D., Függer, M., Posch, M., Schmid, U., Steininger, A., Lenzen, C. (2014). Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip. Journal of Computer and System Sciences, 80(4), 860–900. Peer-reviewed.
  DOI: 10.1016/j.jcss.2014.01.001
• Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., Kowalewski, S. (2014). Runtime verification of microcontroller binary code. Science of Computer Programming, 80, 109–129. Peer-reviewed.
  DOI: 10.1016/j.scico.2012.10.015
• Dolev, D., Függer, M., Schmid, U., Lenzen, C. (2014). Fault-tolerant Algorithms for Tick-generation in Asynchronous Logic: Robust Pulse Generation. Journal of the ACM, 61(5), 1–74. Peer-reviewed.
  DOI: 10.1145/2560561
• Moser, H., Schmid, U. (2014). Reconciling fault-tolerant distributed algorithms and real-time computing. Distributed Computing, 27(3), 203–230. Peer-reviewed.
  DOI: 10.1007/s00446-013-0204-1
• Biely, M., Robinson, P., Schmid, U. (2014). The Generalized Loneliness Detector and Weak System Models for k-Set Agreement. IEEE Transactions on Parallel and Distributed Systems, 25(4), 1078–1088. Peer-reviewed.
  DOI: 10.1109/tpds.2013.77
• Gmeiner, A., Konnov, I., Schmid, U., Veith, H., Widder, J. (2014). Tutorial on Parameterized Model Checking of Fault-Tolerant Distributed Algorithms. In Formal Methods for Executable Software Models (pp. 122–171). Springer.
  DOI: 10.1007/978-3-319-07317-0_4
• Schmid, U. (2014). Final Report FWF FATAL-Project (P21694) (TUW-235380).
  HDL: 20.500.12708/38307
• Schmid, U. (2014). FWF-Proposal ADynNet: Gracefully Degrading Agreement in Directed Dynamic Networks (TUW-235381).
  HDL: 20.500.12708/38308
• Maier, J., Steininger, A. (2014). Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic. In 17th International Symposium on Design and Diagnostics of Electronic Circuits Systems (pp. 33–38). Institute of Electrical and Electronics Engineers (IEEE).
  DOI: 10.1109/DDECS.2014.6868759 / Download: PDF
• Naqvi, S. R., Lechner, J., Steininger, A. (2014). Protection of Muller-Pipelines from transient faults. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium Exhibit on Quality Electronic Design, Santa Clara, United States of America (the). Peer-reviewed.
  DOI: 10.1109/isqed.2014.6783315
• Veeravalli, V. S., Steininger, A., Schmid, U. (2014). Measuring SET pulsewidths in logic gates using digital infrastructure. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium Exhibit on Quality Electronic Design, Santa Clara, United States of America (the). Peer-reviewed.
  DOI: 10.1109/isqed.2014.6783331
• Veeravalli, V. S., Steininger, A. (2014). Architecture for monitoring SET propagation in 16-bit Sklansky adder. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium Exhibit on Quality Electronic Design, Santa Clara, United States of America (the). Peer-reviewed.
  DOI: 10.1109/isqed.2014.6783354
• Veeravalli, V. S., Steininger, A. (2014). Diagnosis of SET Propagation in Combinational Logic under Dynamic Operation. In Proceedings 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10) (p. 6). Peer-reviewed.
  HDL: 20.500.12708/55130
• Anghel, L., Veeravalli, V. S., Alexandrescu, D., Steininger, A., Schneider, K., Costenaro, E. (2014). Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum. In Proceedings 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10) (p. 6). Peer-reviewed.
  HDL: 20.500.12708/55131
• Naqvi, S. R., Steininger, A. (2014). A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments. In Proceedings Design Automation &Test in Europe (p. 6). Peer-reviewed.
  HDL: 20.500.12708/55132
• Sastry, S., Widder, J. (2014). Solvability-Based Comparison of Failure Detectors. In 2014 IEEE 13th International Symposium on Network Computing and Applications. International Symposium on Network Computing and Applications (NCA), Boston, United States of America (the). IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/nca.2014.46
• Konnov, I., Veith, H., Widder, J. (2014). On the Completeness of Bounded Model Checking for Threshold-Based Distributed Algorithms: Reachability. In CONCUR 2014 – Concurrency Theory (pp. 125–140). Peer-reviewed.
  DOI: 10.1007/978-3-662-44584-6_10
• Drăgoi, C., Henzinger, T. A., Veith, H., Widder, J., Zufferey, D. (2014). A Logic-Based Framework for Verifying Consensus Algorithms. In Verification, Model Checking, and Abstract Interpretation 15th International Conference, VMCAI 2014, San Diego, CA, USA, January 19-21, 2014, Proceedings (pp. 161–181). Springer / LNCS. Peer-reviewed.
  DOI: 10.1007/978-3-642-54013-4_10
• Deutsch, T., Widder, J. (2014). Approaching Verification and Validation Challenges in Smart Grids. In Tagungsband ComForEn 2014 (p. 6). Eigenverlag des Österreich isch en Verbandes für Elektrotec h nik.
  HDL: 20.500.12708/55738
• Steininger, A., Veeravalli, V. S., Alexandrescu, D., Costenaro, E., Anghel, L. (2014). Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. In 2014 IEEE 32nd International Conference on Computer Design (ICCD). 2014 32nd IEEE International Conference on Computer Design (ICCD), Seoul, Korea (the Republic of). IEEE. Peer-reviewed.
  DOI: 10.1109/iccd.2014.6974663 / Project: EASET
• Veeravalli, V. S., Steininger, A. (2014). Long term on-chip monitoring of SET pulsewidths in a fully digital ASIC. In 22nd Austrian Workshop on Microelectronics (Austrochip). 22nd Austrian Workshop on Microelectronics, Graz, Austria. IEEE. Peer-reviewed.
  DOI: 10.1109/austrochip.2014.6946318 / Project: EASET
• Najvirt, R., Steininger, A. (2014). Equivalence of clock gating and synchronization with applicability to GALS communication. In 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, Isles Balears, Spain. IEEE. Peer-reviewed.
  DOI: 10.1109/patmos.2014.6951873
• Pavlogiannis, A., Chatterjee, K., Schmid, U., Kößler, A. (2014). A Framework for Automated Competitive Analysis of On-line Scheduling of Firm-Deadline Tasks. In 2014 IEEE Real-Time Systems Symposium. 35th IEEE Real-Time Systems Symposium, Rome, Italy. Peer-reviewed.
  DOI: 10.1109/rtss.2014.9
• Schwarz, M., Winkler, K., Schmid, U., Biely, M., Robinson, P. (2014). Brief announcement. In Proceedings of the 2014 ACM symposium on Principles of distributed computing - PODC ’14. 33th ACM SIGACTSIGOPS Symposium on Principles of Distributed Computing (PODC), Paris, France. ACM. Peer-reviewed.
  DOI: 10.1145/2611462.2611506

2013

• Charron-Bost, B., Gaillard, A., Welch, J. L., Widder, J. (2013). Link Reversal Routing with Binary Link Labels: Work Complexity. SIAM Journal on Computing, 42(2), 634–661. Peer-reviewed.
  DOI: 10.1137/110843095
• Reinbacher, T., Függer, M., Brauer, J. (2013). Runtime verification of embedded real-time systems. Formal Methods in System Design, 44(3), 203–239. Peer-reviewed.
  DOI: 10.1007/s10703-013-0199-z / Project: CEVTES
• Nowak, T., Függer, M., Kößler, A. (2013). On the performance of a retransmission-based synchronizer. Theoretical Computer Science, 509, 25–39. Peer-reviewed.
  DOI: 10.1016/j.tcs.2012.04.035
• Veeravalli, V. S., Polzer, T., Schmid, U., Steininger, A., Hofbauer, M., Schweiger, K., Dietrich, H., Schneider-Hornstein, K., Zimmermann, H., Voss, K.-O., Merk, B., Hajek, M. (2013). An infrastructure for accurate characterization of single-event transients in digital circuits. Microprocessors and Microsystems, 37, 772–791. Peer-reviewed.
  HDL: 20.500.12708/156041
• Hofbauer, M., Schweiger, K., Zimmermann, H., Giesen, U., Langner, F., Schmid, U., Steininger, A. (2013). Supply Voltage Dependent On-Chip Single-Event Transient Pulse Shape Measurements in 90-nm Bulk CMOS Under Alpha Irradiation. IEEE Transactions on Nuclear Science, 60(4), 2640–2646. Peer-reviewed.
  HDL: 20.500.12708/156043
• Charron-Bost, B., Merz, S., Rybalchenko, A., Widder, J. (Eds.). (2013). Formal Verification of Distributed Algorithms. Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany.
  DOI: 10.4230/DagRep.3.4.1
• Schwarz, M., Winkler, K., Schmid, U., Biely, M., Robinson, P. (2013). Gracefully Degrading Consensus and k-set Agreement under Dynamic Link Failures (TUW-220473).
  HDL: 20.500.12708/37755
• Schmid, U. (2013). Final Report FWF PSRTS-Project (P20529) (TUW-235379).
  HDL: 20.500.12708/38306
• Lechner, J., Najvirt, R. (2013). A Generic Architecture for Robust Asynchronous Communication Links. In Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (pp. 121–130). Lecture Notes in Computer Science. Peer-reviewed.
  HDL: 20.500.12708/54501
• Polzer, T., Steininger, A., Lechner, J. (2013). Muller C-Element Metastability Containment. In Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (pp. 103–112). Lecture Notes in Computer Science. Peer-reviewed.
  HDL: 20.500.12708/54509
• John, A., Konnov, I., Schmid, U., Veith, H., Widder, J. (2013). Towards Modeling and Model Checking Fault-Tolerant Distributed Algorithms. In Model Checking Software (pp. 209–226). LNCS, Springer. Peer-reviewed.
  DOI: 10.1007/978-3-642-39176-7_14
• John, A., Konnov, I., Schmid, U., Veith, H., Widder, J. (2013). Parameterized model checking of fault-tolerant distributed algorithms by abstraction. In FMCAD (pp. 201–209). Peer-reviewed.
  HDL: 20.500.12708/54827
• John, A., Konnov, I., Schmid, U., Veith, H., Widder, J. (2013). Brief announcement. In Proceedings of the 2013 ACM symposium on Principles of distributed computing - PODC ’13. ACM SIGACT-SIGOPS Symposium on Principles of Distributed Computing (PODC), Montreal, Canada. ACM. Peer-reviewed.
  DOI: 10.1145/2484239.2484285
• Dolev, D., Lenzen, C., Függer, M., Schmid, U., Perner, M. (2013). HEX. In Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures. SPAA ’13, Montreal, Canada. ACM. Peer-reviewed.
  DOI: 10.1145/2486159.2486192
• Függer, M., Kößler, A., Nowak, T., Schmid, U., Zeiner, M. (2013). The Effect of Forgetting on the Performance of a Synchronizer. In Algorithms for Sensor Systems (pp. 185–200). Peer-reviewed.
  DOI: 10.1007/978-3-642-45346-5_14
• Perner, M., Schmid, U., Lenzen, C., Sigl, M. (2013). Byzantine Self-Stabilizing Clock Distribution with HEX: Implementation, Simulation, Clock Multiplication. In Proceedings of the 6th IARA International Conference on Dependability (DEPEND’13) (pp. 6–15). IARA. Peer-reviewed.
  HDL: 20.500.12708/54927
• Lenzen, C., Függer, M., Hofstätter, M., Schmid, U. (2013). Efficient Construction of Global Time in SoCs Despite Arbitrary Faults. In 2013 Euromicro Conference on Digital System Design. 16th Euromicro Conference on Digital System Design (DSD 2013), Santander, Spain. Digital System Design (DSD), 2013 Euromicro Conference on. Peer-reviewed.
  DOI: 10.1109/dsd.2013.97
• Charron-Bost, B., Függer, M., Nowak, T. (2013). Transience Bounds for Distributed Algorithms. In Formal Modeling and Analysis of Timed Systems 11th International Conference, FORMATS 2013, Buenos Aires, Argentina, August 29-31, 2013, Proceedings (pp. 77–90). Lecture Notes in Computer Science. Peer-reviewed.
  DOI: 10.1007/978-3-642-40229-6_6
• Függer, M., Nowak, T., Schmid, U. (2013). Unfaithful Glitch Propagation in Existing Binary Circuit Models. In 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems. 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2013), Santa Monica, United States of America (the). Peer-reviewed.
  DOI: 10.1109/async.2013.9
• Polzer, T., Steininger, A. (2013). SET Propagation in Micropipelines. In 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013) (p. 8). Peer-reviewed.
  HDL: 20.500.12708/54998
• Naqvi, S. R., Steininger, A., Lechner, J. (2013). An SET Tolerant Tree Arbiter Cell. In Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on (p. 9). Peer-reviewed.
  HDL: 20.500.12708/55001
• Resch, S., Steininger, A., Scherrer, C. (2013). Software Composability and Mixed Criticality for Triple Modular Redundant Architectures. In Proceedings of the 2013 SASSUR Workshop (p. 4). Peer-reviewed.
  HDL: 20.500.12708/55002
• Najvirt, R., Veeravalli, V. S., Steininger, A. (2013). Particle Strikes in C-Gates: Relevance of SET Shapes. In Proceedings of the MEDIAN Workshop 2013 (p. 4). Peer-reviewed.
  HDL: 20.500.12708/55003
• Veeravalli, V. S., Steininger, A. (2013). Performance of Radiation Hardening Techniques under Voltage and Temperature Variations. In Proc. 2013 IEEE Aerospace Conference (p. 6). Peer-reviewed.
  HDL: 20.500.12708/55004
• Najvirt, R., Naqvi, S. R., Steininger, A. (2013). Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs. In Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on (p. 9). Peer-reviewed.
  HDL: 20.500.12708/55005
• Naqvi, S. R., Najvirt, R., Steininger, A. (2013). A Multi-Credit Flow Control Scheme for Asynchronous NoCs. In Proc. 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (p. 6). Peer-reviewed.
  HDL: 20.500.12708/55006
• Polzer, T., Steininger, A. (2013). An Approach for Efficient Metastability Characterization of FPGAs through the Designer. In 19th IEEE International Symposium on Asynchronous Circuits and Systems (p. 9). Peer-reviewed.
  HDL: 20.500.12708/55021
• Polzer, T., Steininger, A. (2013). Metastability Characterization for Muller C-Elements. In 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013) (p. 8). Peer-reviewed.
  HDL: 20.500.12708/55023
• Polzer, T., Steininger, A. (2013). Digital Late-Transition Metastability Simulation Model. In Proceedings of the 16th Euromicro Conference on Digital System Design (p. 8). Peer-reviewed.
  HDL: 20.500.12708/55024
• Chatterjee, K., Kößler, A., Schmid, U. (2013). Automated Analysis of Real-Time Scheduling using Graph Games. In Proceedings 16th ACM International Conference on Hybrid Systems: Computation and Control (HSCC’13) (pp. 163–172). ACM. Peer-reviewed.
  HDL: 20.500.12708/55031

2012

• Widder, J., Biely, M., Gridling, G., Weiss, B., Blanquart, J.-P. (2012). Consensus in the presence of mortal Byzantine faulty processes. Distributed Computing, 24(6), 299–321. Peer-reviewed.
  DOI: 10.1007/s00446-011-0147-3
• Hofbauer, M., Schweiger, K., Dietrich, H., Zimmermann, H., Voss, K.-O., Merk, B., Schmid, U., Steininger, A. (2012). Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating Through a 90 nm Bulk CMOS Inverter Chain. IEEE Transactions on Nuclear Science, 59(6), 2778–2784. Peer-reviewed.
  DOI: 10.1109/tns.2012.2223233
• Függer, M., Schmid, U. (2012). Reconciling fault-tolerant distributed computing and systems-on-chip. Distributed Computing, 24(6), 323–355. Peer-reviewed.
  DOI: 10.1007/s00446-011-0151-7
• Hofbauer, M., Schweiger, K., Dietrich, H., Zimmermann, H., Schmid, U., Giesen, U. (2012). Messung der Auswirkungen von ionisierender Strahlung auf 90 nm CMOS Schaltungen.
  HDL: 20.500.12708/37567
• Függer, M., Widder, J. (2012). Efficient Checking of Link-Reversal-Based Concurrent Systems. In CONCUR 2012- Concurrency Theory 23rd International Conference, CONCUR 2012, Newcastle upon Tyne, September 4-7, 2012. Proceedings (pp. 486–499). Lecture Notes in Computer Science. Springer Verlag. Peer-reviewed.
  DOI: 10.1007/978-3-642-32940-1_34
• Függer, M., Kößler, A., Nowak, T., Zeiner, M. (2012). Brief Announcement: The Degrading Effect of Forgetting on a Synchronizer. In Stabilization, Safety, and Security of Distributed Systems (pp. 90–91). Lecture Notes in Computer Science. Peer-reviewed.
  HDL: 20.500.12708/54498
• Reinbacher, T., Függer, M., Brauer, J. (2012). Real-Time Runtime Verification on Chip. In Proc. of RV 2012: the 3rd International Conference on Runtime Verification. RV 2012: the 3rd International Conference on Runtime Verification, Istanbul, Turkey. LNCS / Springer. Peer-reviewed.
  HDL: 20.500.12708/54500 / Project: CEVTES
• Naqvi, S. R. (2012). An Asynchronous Router Architecture using Four-Phase Bundled Handshake Protocol. In Proc. of The Seventh International Multi-Conference on Computing in the Global Information Technology (p. 6). Peer-reviewed.
  HDL: 20.500.12708/54502
• Naqvi, S. R., Veeravalli, V. S., Steininger, A. (2012). Protecting an Asynchronous NoC against Transient Channel Faults. In Proc. of 15th Euromicro Conference on Digital System Design (p. 8). Peer-reviewed.
  HDL: 20.500.12708/54503
• Lechner, J. (2012). Designing Robust GALS Circuits with Triple Modular Redundancy. In Dependable Computing Conference (EDCC), 2012 Ninth European (pp. 227–236). Peer-reviewed.
  HDL: 20.500.12708/54525
• Lechner, J., Lampacher, M., Polzer, T. (2012). A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding. In Application of Concurrency to System Design (ACSD), 2012 12th International Conference on (pp. 122–131). Peer-reviewed.
  HDL: 20.500.12708/54526
• Lechner, J., Lampacher, M. (2012). Protecting Pipelined Asynchronous Communication Channels Against Single Event Upsets. In Computer Design (ICCD), 2012 IEEE 30th International Conference on (pp. 480–481). Peer-reviewed.
  HDL: 20.500.12708/54527
• Sastry, S., Welch, J. L., Widder, J. (2012). Wait-Free Stabilizing Dining Using Regular Registers. In Principles of Distributed Systems 16th International Conference, OPODIS 2012, Rome, Italy, December 18-20, 2012, Proceedings (pp. 284–299). LNCS / Springer. Peer-reviewed.
  DOI: 10.1007/978-3-642-35476-2_20
• Biely, M., Robinson, P., Schmid, U. (2012). Agreement in Directed Dynamic Networks. In Proceedings 19th International Colloquium on Structural Information and Communication Complexity (SIROCCO’12) (pp. 73–84). Peer-reviewed.
  HDL: 20.500.12708/54563
• Veeravalli, V. S., Steininger, A., Schmid, U., Polzer, T. (2012). Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. In Proceedings 15th Euromicro Symposium on Digital System Design: Architectures, Methods and Tools (DSD’12) (pp. 8–17). Peer-reviewed.
  HDL: 20.500.12708/54564
• Hofbauer, M., Schweiger, K., Zimmermann, H., Giesen, U., Langner, F., Schmid, U., Steininger, A. (2012). Supply Voltage Dependent On-chip Single Event Transient Pulse Shape Measurements in 90 nm Bulk CMOS under Alpha Irradiation. In Proceedings 21st European Conference on Radiation and its Effects on Components and Systems (RADECS’12). 21st European Conference on Radiation and its Effects on Components and Systems (RADECS’12), Biarritz, FRANCE, EU. Peer-reviewed.
  HDL: 20.500.12708/54565
• Reinbacher, T., Horauer, M., Steininger, A. (2012). A Runtime Verification Unit for Microcontrollers. In System, Software, SoC and Silicon Debug Conference (S4D), 2012 (pp. 1–6). Peer-reviewed.
  HDL: 20.500.12708/54566 / Project: CEVTES
• Reinbacher, T., Geist, J., Moosbrugger, P., Horauer, M., Steininger, A. (2012). Parallel Runtime Verification of Temporal Properties for Embedded Software. In Mechatronics and Embedded Systems and Applications (MESA), 2012 IEEE/ASME International Conference on (pp. 224–231). Peer-reviewed.
  HDL: 20.500.12708/54567 / Project: CEVTES
• Veeravalli, V. S., Steininger, A. (2012). Monitoring Single Event Transient Effects in Dynamic Mode. In 1st Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2012) (pp. 51–54). Peer-reviewed.
  HDL: 20.500.12708/54568
• Veeravalli, V. S., Steininger, A. (2012). Radiation-Tolerant Combinational Gates - An Implementation Based Comparison. In Design and Diagnostics of Electronic Circuits Systems (DDECS), 2012 IEEE 15th International Symposium on (pp. 115–120). Peer-reviewed.
  HDL: 20.500.12708/54570
• Fritz, B., Veeravalli, V. S., Steininger, A. (2012). Reliable Gateway for Radiation Experiments on a VLSI Chip. In Austrochip 2012 (pp. 65–70). Peer-reviewed.
  HDL: 20.500.12708/54571
• Veeravalli, V. S., Steininger, A. (2012). LFSR Implementation Using C-Elements. In MEMICS 2012 (pp. 73–83). Peer-reviewed.
  HDL: 20.500.12708/54572
• Veeravalli, V. S., Steininger, A. (2012). Efficient Radiation-Hardening of a Muller C-Element. In 2012 Single Event Effects Symposium. 2012 Single Event Effects Symposium (SEE 2012), San Diego, United States of America (the). Peer-reviewed.
  HDL: 20.500.12708/54573
• Milbredt, P., Glass, M., Lukasiewycz, M., Steininger, A., Teich, J. (2012). Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach. In Design, Automation Test in Europe Conference Exhibition (DATE 2012) Proceedings (pp. 276–279). EDAA. Peer-reviewed.
  HDL: 20.500.12708/54574
• Hofbauer, M., Schweiger, K., Dietrich, H., Zimmermann, H., Schmid, U., Merk, B. (2012). Single Event Effect Measurements in 90nm CMOS Circuits at the Microbeam Facility for the Project FATAL. In GSI Scientific Report 2011 (p. 424). GSI Helmholtzzentrum für Schwerionenforschung GmbH.
  HDL: 20.500.12708/73103

2011

• Steininger, A., Tummeltshammer, P. (2011). Replicated processors on a single die - How independently do they fail? Elektrotechnik Und Informationstechnik : E i, 128(6), 245–250. Peer-reviewed.
  DOI: 10.1007/s00502-011-0005-9
• Ferringer, M. (2011). On Self-Timed Circuits in Real-Time Systems. International Journal of Reconfigurable Computing, 2011, 1–16.
  DOI: 10.1155/2011/972375 / Project: ARTS
• Fuchs, G., Steininger, A. (2011). VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation. Journal of Electrical and Computer Engineering, 2011. Peer-reviewed.
  DOI: 10.1155/2011/936712 / Project: DARTS
• Biely, M., Schmid, U., Weiss, B. (2011). Synchronous consensus under hybrid process and link failures. Theoretical Computer Science, 412(40), 5602–5630. Peer-reviewed.
  DOI: 10.1016/j.tcs.2010.09.032
• Robinson, P., Schmid, U. (2011). The Asynchronous Bounded-Cycle Model. Theoretical Computer Science, 412(40), 5580–5601. Peer-reviewed.
  DOI: 10.1016/j.tcs.2010.08.001
• Ferringer, M. (2011). Conversion of two- to four-phase delay-insensitive asynchronous circuits. In 2011 IEEE EUROCON - International Conference on Computer as a Tool. EUROCON 2011, Lisbon, EU. Peer-reviewed.
  DOI: 10.1109/eurocon.2011.5929318 / Project: ARTS
• Ferringer, M. (2011). Conversion and interfacing techniques for asynchronous circuits. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011), Cottbus, Germany, EU. Peer-reviewed.
  DOI: 10.1109/ddecs.2011.5783039 / Project: ARTS
• Ferringer, M. (2011). Investigating the impact of process variations on an asynchronous Time-Triggered-Protocol controller. In 2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops (DSN-W). Dependable Systems and Networks Workshops (DSN-W), 2011 IEEE/IFIP 41st International Conference on, Hong-Kong, Non-EU. Peer-reviewed.
  DOI: 10.1109/dsnw.2011.5958834 / Project: ARTS
• Charron-Bost, B., Fuegger, M., Welch, J. L., Widder, J. (2011). Brief announcement. In Proceedings of the 23rd ACM symposium on Parallelism in algorithms and architectures - SPAA ’11. SPAA ’11, San Jose, California, USA, Non-EU. ACM. Peer-reviewed.
  DOI: 10.1145/1989493.1989510
• Nowak, T., Függer, M., Kößler, A. (2011). On the Performance of a Retransmission-Based Synchronizer. In Structural Information and Communication Complexity (pp. 234–245). Springer Berlin / Heidelberg. Peer-reviewed.
  HDL: 20.500.12708/54033
• Charron-Bost, B., Függer, M., Welch, J. L., Widder, J. (2011). Full Reversal Routing as a Linear Dynamical System. In Structural Information and Communication Complexity (pp. 101–112). Springer Berlin / Heidelberg. Peer-reviewed.
  DOI: 10.1007/978-3-642-22212-2_10
• Charron-Bost, B., Függer, M., Welch, J. L., Widder, J. (2011). Partial is Full. In Structural Information and Communication Complexity (pp. 113–124). Springer Berlin / Heidelberg. Peer-reviewed.
  DOI: 10.1007/978-3-642-22212-2_11
• Dolev, D., Függer, M., Lenzen, C., Schmid, U. (2011). Fault-Tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation. In Stabilization, Safety, and Security of Distributed Systems (pp. 163–177). Springer Berlin / Heidelberg. Peer-reviewed.
  DOI: 10.1007/978-3-642-24550-3_14
• Reinbacher, T., Brauer, J., Schachinger, D., Steininger, A., Kowalewski, S. (2011). Automated test-trace inspection for microcontroller binary code. In Runtime Verification (pp. 239–244). Peer-reviewed.
  HDL: 20.500.12708/54078 / Project: CEVTES
• Reinbacher, T., Brauer, J. (2011). Precise control flow reconstruction using boolean logic. In Proceedings of the ninth ACM international conference on Embedded software - EMSOFT ’11. EMSOFT2011, ACM international conference on Embedded software, Taipei, Non-EU. ACM New York. Peer-reviewed.
  DOI: 10.1145/2038642.2038662 / Project: CEVTES
• Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., Kowalewski, S. (2011). Past Time LTL Runtime Verification for Microcontroller Binary Code. In Formal Methods for Industrial Critical Systems (pp. 37–51). Springer Berlin / Heidelberg. Peer-reviewed.
  DOI: 10.1007/978-3-642-24431-5_5 / Project: CEVTES
• Reinbacher, T., Steininger, A., Müller, T., Horauer, M., Brauer, J., Kowalewski, S. (2011). Hardware support for efficient testing of embedded software. In International Conference on Mechatronic and Embedded Systems and Applications. The 7th ASME/IEEE International Conference on Mechatronic and Embedded Systems and Applications, Washington, Non-EU. ASME. Peer-reviewed.
  HDL: 20.500.12708/54082 / Project: CEVTES
• Reinbacher, T., Gückel, D., Horauer, M. (2011). Testing microcontroller software simulators. In Workshop on Software Language Engineering for Cyber-physical Systems. WS4C 2011, Berlin, EU. Peer-reviewed.
  HDL: 20.500.12708/54083 / Project: CEVTES
• Biely, M., Robinson, P., Schmid, U. (2011). Easy Impossibility Proofs for k-Set Agreement in Message Passing Systems. In OPODIS’11 (pp. 299–312). Springer Berlin / Heidelberg. Peer-reviewed.
  HDL: 20.500.12708/54094
• Biely, M., Robinson, P., Schmid, U. (2011). Solving k-Set Agreement with Stable Skeleton Graphs. In 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum. International Parallel and Distributed Processing Symposium (IPDPS), Denver, United States of America (the). Peer-reviewed.
  DOI: 10.1109/ipdps.2011.301
• Moser, H., Schmid, U. (2011). Reconciling Fault-Tolerant Distributed Algorithms and Real-Time Computing. In Structural Information and Communication Complexity (pp. 42–53). Springer Berlin / Heidelberg. Peer-reviewed.
  DOI: 10.1007/978-3-642-22212-2_5
• Biely, M., Robinson, P., Schmid, U. (2011). Brief Announcement: Easy Impossibility Proofs for k-Set Agreement in Message Passing Systems. In PODC’11 (pp. 227–228). ACM.
  HDL: 20.500.12708/54097

2010

• Charron-Bost, B., Hutle, M., Widder, J. (2010). In search of lost time. Information Processing Letters, 110(21), 928–933. Peer-reviewed.
  DOI: 10.1016/j.ipl.2010.07.017
• Thallner, B., Moser, H., Schmid, U. (2010). Topology Control for Fault-Tolerant Communication in Wireless Ad Hoc Networks. Wireless Networks, 16(2), 387–404. Peer-reviewed.
  DOI: 10.1007/s11276-008-0139-9
• Jeitler, M., Lechner, J. (2010). Low Latency Recovery from Transient Faults for Pipelined Processor Architectures. In 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. DSD 2010 (Euromicro Conference on Digital System Design), Lille, France, EU. IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/dsd.2010.87
• Jeitler, M., Lechner, J., Steininger, A. (2010). Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. In 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria, Austria. IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/ddecs.2010.5491776
• Függer, M., Dielacher, A., Schmid, U. (2010). How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining. In 2010 European Dependable Computing Conference. EDCC - 8 (European Dependable Computing Conference), Valencia, Spain, EU. IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/edcc.2010.35
• Ferringer, M. (2010). Towards self-timed logic in the Time-Triggered Protocol. In 2010 International Conference on Dependable Systems and Networks Workshops (DSN-W). DSN 2010 (International Conference on Dependable Systems and Networks), Chicago, IL, USA, Non-EU. IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/dsnw.2010.5542607 / Project: THETA
• Ferringer, M. (2010). Investigating Self-Timed Circuits for the Time-Triggered Protocol. In Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 (pp. 101–108). KIT Scientific Publishing - DFG. Peer-reviewed.
  HDL: 20.500.12708/53494 / Project: ARTS
• Kößler, A., Moser, H., Schmid, U. (2010). Real-Time Analysis of Round-based Distributed Algorithms. In Proceedings of the 1st International Real-Time Scheduling Open Problems Seminar (pp. 9–11). Peer-reviewed.
  HDL: 20.500.12708/53495
• Chung, H. C., Robinson, P., Welch, J. L. (2010). Brief Announcement: Regional Consecutive Leader Election in Mobile Ad-Hoc Networks. In Algorithms for Sensor Systems (pp. 89–91). Springer. Peer-reviewed.
  DOI: 10.1007/978-3-642-16988-5_8
• Chung, H. C., Robinson, P., Welch, J. L. (2010). Regional consecutive leader election in mobile ad-hoc networks. In Proceedings of the 6th International Workshop on Foundations of Mobile Computing - DIALM-POMC ’10. ACM SIGACT/SIGMOBILE (International Workshop on FOUNDATIONS OF MOBILE COUMPUTING), Cambridge, Massachusetts, USA, Non-EU. ACM. Peer-reviewed.
  DOI: 10.1145/1860684.1860701
• Friesenbichler, W., Panhofer, T., Steininger, A. (2010). A deterministic approach for hardware fault injection in asynchronous QDI logic. In 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria, Austria. IEEE. Peer-reviewed.
  DOI: 10.1109/ddecs.2010.5491758
• Friesenbichler, W., Panhofer, T., Steininger, A. (2010). Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm. In 2010 International Conference on Dependable Systems and Networks Workshops (DSN-W). WSDN 2010 (4th Workshop on Dependable and Secure Nanocomputing, Chicago, IL, USA, Non-EU. IEEE Computer Socitey. Peer-reviewed.
  DOI: 10.1109/dsnw.2010.5542609
• Friesenbichler, W., Panhofer, T., Steininger, A. (2010). Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study. In 2010 NASA/ESA Conference on Adaptive Hardware and Systems. NASA/ESA 2010 (Conference on Adaptive Hardware and Systems), Anaheim, CA, USA, Non-EU. IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/ahs.2010.5546277
• Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., Kowalewski, S. (2010). Test-Case Generation for Embedded Binary Code Using Abstract Interpretation. In MEMICS proceedings (pp. 151–158). Peer-reviewed.
  HDL: 20.500.12708/53554 / Project: CEVTES
• Schmid, U. (2010). Synchrony and Time in Fault-Tolerant Distribiuted Algorithms. In Formal Modeling and Analysis of Timed Systems. FORMATS 2010 (Formal Modeling and Analysis of Times Systems), Klosterneuburg, Austria, Austria. Springer.
  HDL: 20.500.12708/53556
• Goiser, A., Khattab, S., Fassl, G., Schmid, U. (2010). A New Robust Interference Reduction Scheme for Low Complexity Direct-Sequence Spread-Spectrum Receivers: Performance. In CTRQ-2010 (p. 7). IEEE Conference Proceedings.
  HDL: 20.500.12708/71631
• Goiser, A. M. J., Khattab, S., Fassl, G., Schmid, U. (2010). A New Robust Interference Reduction Scheme for Low Complexity Direct-Sequence Spread-Spectrum Receivers: Optimization. In 2010 Third International Conference on Communication Theory, Reliability, and Quality of Service. IEEE-Explore, Austria. IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/ctrq.2010.51

2009

• Widder, J., Schmid, U. (2009). The Theta-Model: achieving synchrony without clocks. Distributed Computing, 22(1), 29–47. Peer-reviewed.
  DOI: 10.1007/s00446-009-0080-x
• Biely, M., Widder, J. (2009). Optimal Message-Driven Implementations of Omega with Mute Processes. ACM Transactions on Autonomous and Adaptive Systems, 4(1). Peer-reviewed.
  DOI: 10.1145/1462187.1462191
• Függer, M., Steininger, A., Armengaud, E. (2009). Safely Stimulating the Clock Synchronization Algorithm in Time-Triggered Systems - A Combined Formal and Experimental Approach. IEEE Transactions on Industrial Informatics, 5(2), 132–145. Peer-reviewed.
  HDL: 20.500.12708/166191 / Project: EXTRACT
• Hutle, M., Malkhi, D., Schmid, U., Zhou, L. (2009). Chasing the Weakest System Model for Implementing Ω and Consensus. IEEE Transactions on Dependable and Secure Computing, 6(4), 269–281. Peer-reviewed.
  DOI: 10.1109/tdsc.2008.24
• Schmid, U., Weiss, B., Keidar, I. (2009). Impossibility Results and Lower Bounds For Consensus Under Link Failures. SIAM Journal on Computing, 38(5), 1912–1951. Peer-reviewed.
  DOI: 10.1137/s009753970443999x
• Rahbaran, B., Steininger, A. (2009). Is Asynchronous Logic More Robust Than Synchronous Logic? IEEE Transactions on Dependable and Secure Computing, 6(4), 282–294. Peer-reviewed.
  DOI: 10.1109/tdsc.2008.37
• Birner, M., Handl, T. (2009). ARROW - A Generic Hardware Fault Injection Tool for NoCs. In 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools. DSD 2009 (Euromicro Conference on Digital System Design), Patras, Greece, EU. IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/dsd.2009.223
• Biely, M., Robinson, P., Schmid, U. (2009). Weak Synchrony Models and Failure Detectors for Message Passing (𝑘-)Set Agreement. In T. Abdelzaher, M. Raynal, N. Santoro (Eds.), Principles of Distributed Systems: 13th International Conference, OPODIS 2009, Nîmes, France, December 15-18, 2009. Proceedings (pp. 285–299). Springer. Peer-reviewed.
  DOI: 10.1007/978-3-642-10877-8_23
• Tummeltshammer, P., Steininger, A. (2009). On the role of the power supply as an entry for common cause faults—An experimental analysis. In 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. DDECS 2009 (Design and Diagnostics of Electronic Circuits and Systems), Liberec, Czech Republic, EU. IEEE. Peer-reviewed.
  DOI: 10.1109/ddecs.2009.5012118
• Polzer, T., Handl, T., Steininger, A. (2009). A Metastability-Free Multi-synchronous Communication Scheme for SoCs. In R. Guerraoui F. Petit (Eds.), Stabilization, Safety, and Security of Distributed Systems: 11th International Symposium, SSS 2009, Lyon, France, November 3-6, 2009. Proceedings (pp. 578–592). Springer. Peer-reviewed.
  DOI: 10.1007/978-3-642-05118-0_40 / Project: DARTS
• Biely, M., Robinson, P., Schmid, U. (2009). Brief Announcment: Weak Synchrony Models and Failure Detectors for Message Passing (𝑘-)Set Agreement. In I. Keidar (Ed.), Distributed Computing: 23rd International Symposium, DISC 2009, Elche, Spain, September 23-25, 2009, Proceedings (pp. 360–361). Springer. Peer-reviewed.
  DOI: 10.1007/978-3-642-04355-0_38
• Charron-Bost, B., Gaillard, A., Welch, J., Widder, J. (2009). Routing without ordering. In Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures - SPAA ’09. SPAA 2009 (Parallelism in Algorithms and Architectures), Calgary, Alberta, Canada, Non-EU. ACM. Peer-reviewed.
  DOI: 10.1145/1583991.1584034
• Charron-Bost, B., Welch, J. L., Widder, J. (2009). Link Reversal: How to Play Better to Work Less. In Algorithmic Aspects of Wireless Sensor Networks (pp. 88–101). Springer. Peer-reviewed.
  DOI: 10.1007/978-3-642-05434-1_10
• Ferringer, M. (2009). Coupling Asynchronous Signals into Asynchronous Logic. In Austrochip (pp. 97–102). Institut für Elektronik - TU Graz. Peer-reviewed.
  HDL: 20.500.12708/52854 / Project: ARTS
• Tummeltshammer, P., Steininger, A. (2009). Power Supply Induced Common Cause Faults - Experimental Assessment of Potential Countermeasures. In DSN 2009 - Full Program (pp. 449–457). Springer. Peer-reviewed.
  HDL: 20.500.12708/52864
• Fuchs, G., Függer, M., Steininger, A. (2009). On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme. In 2009 15th IEEE Symposium on Asynchronous Circuits and Systems. ASYNC 2009 (International Symposium on Asynchronous Circuits and Systems), Chapel Hill, North Carolina, Non-EU. IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/async.2009.15 / Project: DARTS
• Dielacher, A., Függer, M. (2009). How to Speed-up Fault-tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining. In PODC’09 (pp. 276–277). ACM. Peer-reviewed.
  HDL: 20.500.12708/52866
• Függer, M., Fuchs, G., Steininger, A. (2009). On the Stability and Robustness of Non-Synchronous Circuits with Timing Loops. In WSDN 2009 (pp. 45–50). Springer. Peer-reviewed.
  HDL: 20.500.12708/52868 / Project: DARTS
• Friesenbichler, W., Steininger, A. (2009). Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic. In 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools. DSD 2009 (Euromicro Conference on Digital System Design), Patras, Greece, EU. IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/dsd.2009.142
• Tummeltshammer, P., Steininger, A. (2009). On the Risk of Fault Coupling over the Chip Substrate. In 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools. DSD 2009 (Euromicro Conference on Digital System Design), Patras, Greece, EU. IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/dsd.2009.185
• Armengaud, E., Steininger, A. (2009). Remote Measurement of Local Oscillator Drifts in FlexRay Networks. In DATE09 (pp. 1082–1087). Springer. Peer-reviewed.
  HDL: 20.500.12708/52872 / Project: EXTRACT
• Steininger, A. (2009). Error Containment in the Presence of Metastability. In Fault-Tolerant Distributed Algorithms on VLSI Chips (p. ?). Leibniz Zentrum Informatik. Peer-reviewed.
  HDL: 20.500.12708/52873
• Charron-Bost, B., Dolev, S., Ebergen, J., Schmid, U. (2009). Fault Tolerant Distribiuted Algorithms and VLSI - An Appetizer. In Fault-Tolerant Distributed Algorithms on VLSI Chips (p. ?). Leibniz Zentrum Informatik.
  HDL: 20.500.12708/52874
• Jeitler, M., Delvai, M., Reichör, S. (2009). FuSE - a hardware accelerated HDL fault injection tool. In 2009 5th Southern Conference on Programmable Logic (SPL). SPL 2009 (Southern Conference on Programmable Logic), Sao Carlos, Brazil, Non-EU. IEEE. Peer-reviewed.
  DOI: 10.1109/spl.2009.4914906
• Jeitler, M., Lechner, J. (2009). Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection. In MEMICS 2009 proceedings (pp. 110–117). Universität Brno. Peer-reviewed.
  HDL: 20.500.12708/52876
• Jeitler, M., Lech, J. (2009). Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation. In 2009 International Conference on Reconfigurable Computing and FPGAs. ReConFig 2009 (International Conference on ReConFigurable Computing and FPGAs), Cancun, Quintana Roo, Mexico, Non-EU. CPS. Peer-reviewed.
  DOI: 10.1109/reconfig.2009.35
• Fuchs, G. (2009). Implications of VLSI Fault Models and Distributed Systems Failure Models --- A Hardware Designer’s View. In Fault-Tolerant Distributed Algorithms on VLSI Chips (p. ?). Leibniz Zentrum Informatik. Peer-reviewed.
  HDL: 20.500.12708/52888 / Project: DARTS
• Biely, M., Hutle, M. (2009). Consensus When All Processes May Be Byzantine for Some Time. In Stabilization, Safety, and Security of Distributed Systems (pp. 120–132). Lecture Notes in Conputer Science / Springer Verlag. Peer-reviewed.
  DOI: 10.1007/978-3-642-05118-0_9

2008

• Armengaud, E., Steininger, A., Horauer, M. (2008). Towards a Systematic Test for Embedded Automotive Communication Systems. IEEE Transactions on Industrial Informatics, 4(3), 146–155. Peer-reviewed.
  DOI: 10.1109/TII.2008.2002704 / Project: STEACS
• Gyimesi, M., Dielacher, A., Handl, T., Wittmann, C. (2008). An Object-oriented Solution to ARGESIM Benchmark C4 “Dining Philosophers Problem” implemented with AnyLogic. Simulation News Europe SNE, 18(1), 31–32.
  HDL: 20.500.12708/171148
• Legourski, V., Huang, Y., Cevan, O., Breitenecker, F. (2008). Statechart Modelling for ARGESIM Benchmark C10 “Dining Philosophers Problem II” using Simulink/Stateflow. Simulation News Europe SNE, 18(1), 39–40.
  HDL: 20.500.12708/171151
• Tauböck, S. M., Jahn, P., Polzer, T., Schuster, A. (2008). An Object-oriented DEV Approach to ARGESIM Benchmark C16 “Restaurant Business Dynamics” using Enterprise Dynamics. Simulation News Europe SNE, 18(1), 41–42.
  HDL: 20.500.12708/171152
• Moser, H. (2008). Towards a real-time distribiuted computing model. Theoretical Computer Science, 410(6–7), 629–659. Peer-reviewed.
  DOI: 10.1016/j.tcs.2008.10.012
• Trödhandl, C., Weiss, B. (2008). A Concept for Hybrid Fault Injection in Distributed Systems. In Testing: Academic and Industrial Conference --- Practice and Research Techniques (Fast Abstracts). Testing: Academic and Industrial Conference --- Practice and Research Techniques, Windsor, United Kingdom, EU. Peer-reviewed.
  HDL: 20.500.12708/52265
• Forster, W., Kutschera, C., Steininger, A., Göschka, K. M. (2008). Automated Generation of Explicit Connectors for Component Based Hardware/Software Interaction in Embedded Real-Time Systems. In Proceedings of the 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS 2008), (IPDPS 2008) (pp. 1–8). IEEE Computer Society. Peer-reviewed.
  HDL: 20.500.12708/52268
• Schmid, U., Robinson, P. (2008). The asynchronous bounded-cycle model. In Proceedings of the twenty-seventh ACM symposium on Principles of distributed computing - PODC ’08. ACM Symposium on Principles of Distributed Computing, Las Vegas, United States of America (the). Association for Computing Machinery (ACM). Peer-reviewed.
  DOI: 10.1145/1400751.1400815
• Robinson, P., Schmid, U. (2008). The Asynchronous Bounded Cycle Model. In Stabilization, Safety, and Security of Distributed Systems. 10 International Symposium on Stabilization, Safety, and Security of Distributed Systems (SSS 2008), Detroit, USA, Non-EU. Lecture Notes in Conputer Science / Springer Verlag. Peer-reviewed.
  DOI: 10.1007/978-3-540-89335-6_20
• Schmid, U. (2008). Keynote: Distributed Algorithms and VLSI. In Stabilization, Safety, and Security of Distributed Systems (pp. 3–3). Lecture Notes in Conputer Science / Springer Verlag.
  DOI: 10.1007/978-3-540-89335-6_3
• Fuchs, G., Függer, M., Schmid, U., Steininger, A. (2008). Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip. In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. 11th EUROMICRO Conference on Digital System Design (DSD 2008), Parma, Italien, EU. IEEE. Peer-reviewed.
  DOI: 10.1109/dsd.2008.65 / Project: DARTS
• Grahsl, J., Handl, T., Steininger, A. (2008). Exploring the Usefulness of the Gate-level Stuck-at Fault Model for Muller C-Elements. In 20. Workshop Testmethoden und Vuverlässigkeit von Schaltungen und Systemen (pp. 165–169). Peer-reviewed.
  HDL: 20.500.12708/52459 / Project: DARTS
• Milbredt, P., Horauer, M., Steininger, A. (2008). An investigation of the clique problem in FlexRay. In 2008 International Symposium on Industrial Embedded Systems. SIES´2008 Third international symposium on industrial embedded systems, Montpellier - La Grande Motte, France, EU. Peer-reviewed.
  DOI: 10.1109/sies.2008.4577700
• Armengaud, E., Függer, M., Steininger, A. (2008). Safe deterministic replay for stimulating the clock synchronization algorithm in time-triggered systems. In 2008 IEEE International Workshop on Factory Communication Systems. WFCS, Turin, Italy. Peer-reviewed.
  DOI: 10.1109/wfcs.2008.4638707 / Project: EXTRACT
• Milbredt, P., Steininger, A., Horauer, M. (2008). Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks. In 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008). IEEE International Workshop on Electronic Design, Test and Applications, Hong-Kong, Non-EU. Peer-reviewed.
  DOI: 10.1109/delta.2008.74
• Ambrosch, K., Humenberger, M., Kubinger, W., Steininger, A. (2008). Extending two non-parametric transforms for FPGA based stereo matching using bayer filtered cameras. In 2008 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops. IEEE Conference on Computer Vision and Pattern Recognition, 2008. CVPR ’08, Anchorage, Alaska, USA, Non-EU. Peer-reviewed.
  DOI: 10.1109/cvprw.2008.4563146
• Friesenbichler, W., Panhofer, T., Delvai, M. (2008). Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits. In 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2008, Bratislava, Slovakia, EU. IEEE. Peer-reviewed.
  DOI: 10.1109/ddecs.2008.4538799
• Panhofer, T., Friesenbichler, W., Delvai, M. (2008). Fault Tolerant Four-State Logic by Using Self-Healing Cells. In 2008 IEEE International Conference on Computer Design (p. 6). IEEE. Peer-reviewed.
  HDL: 20.500.12708/52475
• Khyo, G., Puschner, P., Delvai, M. (2008). An Operating System for a Time-Predictable Computing Node. In Software Technologies for Embedded and Ubiquitous Systems (pp. 150–161). Lecture Notes in Computer Science / Springer Verlag. Peer-reviewed.
  DOI: 10.1007/978-3-540-87785-1_14
• Lechner, J., Delvai, M. (2008). Implementation of a Design Tool for Automated Generation of Four State Logic Circuits. In Proceedings of the Junior Scientist Conference 2008 (pp. 85–86). Peer-reviewed.
  HDL: 20.500.12708/52477
• Moser, H., Schmid, U. (2008). Optimal Deterministic Remote Clock Estimation in Real-Time Systems. In Principles of Distributed Systems (pp. 363–387). Lecture Notes in Computer Science / Springer Verlag. Peer-reviewed.
  DOI: 10.1007/978-3-540-92221-6_24
• Hepp, S., Klima, G., Kadlec, A., Krammer, L., Luckner, W., Prokesch, D., Resch, S., Wasicek, A., Wilhelm, J., Tummeltshammer, P., Delvai, M. (2008). Exploring Hardware Software Partitioning on the Example of a Fingerprint Verification System. In Proc. of the 16th Austrian Workshop on Microelectronics 2008 (pp. 7–12). Peer-reviewed.
  HDL: 20.500.12708/52482
• Armengaud, E. (2008). Experimental Evaluation of the FlexRay Clock Synchronization Service. In 20. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (pp. 85–89).
  HDL: 20.500.12708/52483 / Project: EXTRACT

2007

• Schmid, U., Steininger, A., Sust, M. (2007). FIT-IT Projekt DARTS: Dezentrale fehlertolerante Taktgenerierung. Elektrotechnik und Informationstechnik : e i, 124(1–2), 3–8. Peer-reviewed.
  DOI: 10.1007/s00502-006-0409-0
• Tummeltshammer, P., Hoe, James. C., Pueschel, M. (2007). Time-Multiplexed Multiple Constant Multiplication. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (pp. 1551–1563). IEEE. Peer-reviewed.
  HDL: 20.500.12708/25411
• Widder, J., Schmid, U. (2007). Booting Clock Synchronization in Partially Synchronous Systems with Hybrid Process and Link Failures. In Distributed Computing (pp. 115–140). Springer-Verlag. Peer-reviewed.
  HDL: 20.500.12708/25412
• Handl, T., Steininger, A., Kempf, G. (2007). An Efficient Test Strategy for a Fault-Tolerant Clock Generator for Systems-on-Chip. In 19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (pp. 66–70). Peer-reviewed.
  HDL: 20.500.12708/51796 / Project: DARTS
• Kottke, T., Steininger, A. (2007). Vergleich zweier zwischen Sicherheit und Performanz rekonfigurierbarer Prozessorsysteme. In 19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen. 19. ITG/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Errlangen, EU. Peer-reviewed.
  HDL: 20.500.12708/51797
• Schmid, U., Steininger, A., Veith, H. (2007). Towards a Systematic Design of Fault-Tolerant Asynchronous Circuits. In Fachtagung Zuverlässigkeit und Entwurf (pp. 173–174). VDE Verlag. Peer-reviewed.
  HDL: 20.500.12708/51805
• Biely, M., Charron-Bost, B., Gaillard, A., Hutle, M., Schiper, A., Widder, J. (2007). Tolerating Corrupted Communication. In 26th ACM Symposium on Principles of Distributed Computing (PODC’07) (pp. 244–253). Peer-reviewed.
  HDL: 20.500.12708/52017
• Biely, M., Hutle, M., Penso, L. D., Widder, J. (2007). Relating Stabilizing Timing Assumptions to Stabilizing Failure Detectors Regarding Solvability and Efficiency. In stabilization. Ninth International Symposium on Stabilization, Safety, and Security of Distributed Systems (SSS 2007), Paris, EU. Peer-reviewed.
  HDL: 20.500.12708/52032
• Widder, J., Gridling, G., Weiss, B., Blanquart, J.-P. (2007). Synchronous Consensus with Mortal Byzantines. In Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks. IEEE Conference on Dependable Systems and Networks (DSN), Philadelphia, PA, United States of America (the). Peer-reviewed.
  HDL: 20.500.12708/52033
• Grahsl, J., Handl, T., Steininger, A., Kempf, G. (2007). SAFE - A Scalable Environment for Automated Transistor Level Fault Effect Analysis. In Austrochip - Workshop on Microelectronics (pp. 91–98). Peer-reviewed.
  HDL: 20.500.12708/52053 / Project: DARTS
• Delvai, M., Panhofer, T. (2007). SELF-HEALING CIRCUITS FOR SPACE-APPLICATIONS. In Proceedings of 17th INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (pp. 505–506). Peer-reviewed.
  HDL: 20.500.12708/52054
• Handl, T., Steininger, A., Kempf, G. (2007). Adopting the Scan Approach for a Fault Tolerant Asynchronous Clock Generation Circuit. In Proceedings IDT’07 - The Second International Design and Test Workshop (pp. 115–119). Peer-reviewed.
  HDL: 20.500.12708/52055 / Project: DARTS
• Armengaud, E., Forster, W. (2007). A Novel Interconnection Approach for Globally Asynchronous Locally Synchronous Circuits. In Austrochip - Workshop on Microelectronics (pp. 107–113). Peer-reviewed.
  HDL: 20.500.12708/52060
• Armengaud, E., Steininger, A., Hanzlik, A. (2007). The Effect of Quartz Drift on Convergence-Average based Clock Synchronization. In Proceedings of the 12th IEEE Conference on Emerging Technologies and Factory Automation (pp. 1123–1130). Peer-reviewed.
  HDL: 20.500.12708/52061 / Project: EXTRACT
• Angerer, C., Cevan, O., Fauster, L., Huang, Y., Huber, B., Legourski, V., Pirker, S., Polzer, T., Reichhard, D., Rigler, D., Schuster, A., Weirich, B., Tummeltshammer, P., Delvai, M. (2007). Exploring Hardware Software Partitioning on the Example of a Face Recognition System. In Austrochip - Workshop on Microelectronics (pp. 121–127). Peer-reviewed.
  HDL: 20.500.12708/52062
• Kottke, T., Steininger, A. (2007). A Fail-Silent Reconfigurable Superscalar Processor. In 13th Pacific Rim International Symposium on Dependable Computing (PRDC’07), Melbourne (pp. 232–239). Peer-reviewed.
  HDL: 20.500.12708/52063
• Horauer, M., Armengaud, E., Steininger, A. (2007). Concepts and Tools for the Test of the Communication Sub-System of Time-Triggered Distributed Embedded Systems. In ASME 2007 International Conference on Design Engineering Technical Conferences Computers and Information in Engineering. International Conference on Design Engineering Technical Conferences Computers and Information in Engineering (ASME), Las Vegas, Non-EU. Peer-reviewed.
  HDL: 20.500.12708/52064 / Project: STEACS
• Ambrosch, K., Humenberger, M., Kubinger, W., Steininger, A. (2007). Hardware Implementation of an SAD based stereo vision algorithm. In Proceedings of Third IEEE Workshop on Embedded Computer Vision. Third IEEE Workshop on Embedded Computer Vision, Minneapolis, Non-EU. Peer-reviewed.
  HDL: 20.500.12708/52065
• Anceaume, E., Delporte-Gallet, C., Fauconnier, H., Hurfin, M., Widder, J. (2007). Clock Synchronization in the Byzantine-Recovery Failure Model. In International Conference On Principles Of DIstributed System (pp. 90–104). Peer-reviewed.
  HDL: 20.500.12708/52073
• Schmid, U. (2007). A Perspective of Fault-Tolerant Clock Synchronization. In IEEE Symposium on Precision Clock Synchronization for Measurement, Control and Communication. 2007 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication, Vienna, Austria.
  HDL: 20.500.12708/52101
• Schmid, U. (2007). LTCC: a fascinating technology platform for miniaturized devices. In T. Becker, C. Cané, N. S. Barker (Eds.), Smart Sensors, Actuators, and MEMS III (Proceedings Volume). SPIE.
  DOI: 10.1117/12.722793

2006

• Losert, T., Huber, W., Hendling, K., Jandl, M. (2006). A CORBA-Based Architecture for Hard Real-Time Systems. In Intelligent Systems at the Service of Mankind - Volume II (pp. 239–254). Ubooks. Peer-reviewed.
  HDL: 20.500.12708/25006
• Hendling, K., Losert, T., Jandl, M. (2006). An Intelligent Interference-Minimizing Routing Algorithm. In W. Huber (Ed.), Intelligent Systems at the Service of Mankind - Volume II (pp. 187–204). Ubooks. Peer-reviewed.
  HDL: 20.500.12708/25007
• Delvai, M., Steininger, A. (2006). Teaching Hardware Software Codesign to Software Engineers. In International Workshop on Reconfigurable Computing Education. 1st International Workshop on Reconfigurable Computing Education, Karlsruhe, EU. Peer-reviewed.
  HDL: 20.500.12708/51473
• Steininger, A., Kottke, T. (2006). Ein dynamisch rekonfigurierbarer superskalarer Prozessor mit den Modi Sicherheit und Performanz. In 18. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (pp. 36–40). Peer-reviewed.
  HDL: 20.500.12708/51501
• Kottke, T., Steininger, A. (2006). A Reconfigurable Generic Dual-Core Architecture. In Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN) (pp. 45–54). Peer-reviewed.
  HDL: 20.500.12708/51502
• Fuchs, G., Függer, M., Steininger, A., Zangerl, F. (2006). Analysis of Constraints in a Fault-Tolerant Distributed Clock Generation Scheme. In WDES 2006 3rd Workshop on Dependable Embedded Systems (pp. 22–27). Peer-reviewed.
  HDL: 20.500.12708/51503 / Project: DARTS
• Steininger, A., Handl, T., Fuchs, G., Zangerl, F. (2006). Testing the Hardware Implementation of a Distributed Clock Generation Algorithm for SoCs. In East-West Design Test International Workshop (pp. 59–64). Peer-reviewed.
  HDL: 20.500.12708/51504 / Project: DARTS
• Függer, M., Handl, T., Steininger, A., Widder, J., Tögel, C. (2006). An Efficient Test for a Transition Signalling based Up-/Down-Counter. In Austrochip Mikroelektroniktagung (pp. 55–62). Peer-reviewed.
  HDL: 20.500.12708/51505 / Project: DARTS
• Fuchs, G., Grahsl, J., Schmid, U., Steininger, A., Kempf, G. (2006). Threshold Modules -- Die Schlüsselelemente zur Verteilten Generierung eines Fehlertoleranten Taktes. In Austrochip Mikroelektroniktagung (pp. 149–156). Peer-reviewed.
  HDL: 20.500.12708/51506 / Project: DARTS
• Függer, M., Schmid, U., Fuchs, G., Kempf, G. (2006). Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip. In EDCC-6 (pp. 87–96). Peer-reviewed.
  HDL: 20.500.12708/51507 / Project: DARTS
• Steininger, A., Függer, M., Schmid, U., Fuchs, G. (2006). Fault-Tolerant Algorithms on SoCs - A case study. In Supplement Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN) (pp. 190–191). Peer-reviewed.
  HDL: 20.500.12708/51508 / Project: DARTS
• Ferringer, M., Fuchs, G., Steininger, A., Kempf, G. (2006). VLSI Implementation of a Fault-Tolerant Distributed Clock Generation. In The 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (pp. 563–571). Peer-reviewed.
  HDL: 20.500.12708/51509 / Project: DARTS
• Armengaud, E. (2006). ExTraCT: A New Approach for the Transparent Test of Time-Triggered Communication Systems. In 18. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen. 18. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Titisee, EU. Peer-reviewed.
  HDL: 20.500.12708/51514 / Project: EXTRACT
• Armengaud, E. (2006). Low Level Bus Traffic Replay for the Test of Time-Triggered Communication Systems. In 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (pp. 155–156). Peer-reviewed.
  HDL: 20.500.12708/51515 / Project: EXTRACT
• Armengaud, E., Steininger, A. (2006). A Remote and Transparent Approach for the Test and Diagnosis of Automotive Networks. In Junior Scientist Conference 2006. Junior Scientist Conference, Wien, Austria. Peer-reviewed.
  HDL: 20.500.12708/51516 / Project: EXTRACT
• Armengaud, E., Steininger, A. (2006). Pushing the Limits of Remote Online Diagnosis in FlexRay Networks. In 6th IEEE International Workshop on Factory Communication Systems. IEEE International Workshop on Factory Communication Systems, Porto, Portugal. Peer-reviewed.
  HDL: 20.500.12708/51517 / Project: EXTRACT
• Armengaud, E., Steininger, A., Horauer, M. (2006). Automatic Parameter Identification in FlexRay Based Automotive Communication Networks. In 11th IEEE International Conference on Emerging Technologies and Factory Automation (pp. 897–904). IEEE. Peer-reviewed.
  DOI: 10.1109/ETFA.2006.355404 / Projects: STEACS, EXTRACT
• Gridling, G., Weiss, B., Elmenreich, W., Trödhandl, C. (2006). Embedded Systems Exams With True/False Questions: A Case Study. In Proceedings of the Second International Conference on Education and Technology (pp. 168–172). Peer-reviewed.
  HDL: 20.500.12708/51519
• Elmenreich, W., Trödhandl, C., Weiss, B. (2006). Embedded Systems Home Experimentation. In Proceedings of the Second International Conference on Education and Technology (pp. 11–15). Peer-reviewed.
  HDL: 20.500.12708/51520
• Trödhandl, C., Proske, M., Elmenreich, W. (2006). Remote Target Monitoring in Embedded Systems Lab Courses using a Sensor Network. In The 32nd Annual Conference of the IEEE Industrial Society - IECON’2006 (pp. 5433–5438). Peer-reviewed.
  HDL: 20.500.12708/51521
• Gridling, G., Weiss, B. (2006). A µController Lab for Distance Learning. In EWME 2006 - Proceedings (pp. 129–132). Peer-reviewed.
  HDL: 20.500.12708/51522
• Biely, M., Widder, J. (2006). Optimal Message-Driven Implementations of Omega with Mute Processes. In Stabilization, Safety, and Security of Distributed Systems (pp. 110–121). Peer-reviewed.
  HDL: 20.500.12708/51523
• Ambrosch, K., Helpa, C., Lechner, J., Leidenfrost, R., Panhofer, T., platschek, A., Ramberger, S., Stadler, U., Steiner, D., Trinkl, H., Widtmann, C., Delvai, M. (2006). Design Variety in Hardware/Software Codesign - Implementations of an AES Encoder. In Austrochip Mikroelektroniktagung (pp. 181–188). Austrochip 2006. Peer-reviewed.
  HDL: 20.500.12708/51525
• Delvai, M., Steininger, A. (2006). Solving the Fundamental Problem of Digital Design -- A Systematic Review of Design Methods. In 9th Euromicro Conference on Digital System Design - Architectures, Methods and Tools (pp. 131–136). Peer-reviewed.
  HDL: 20.500.12708/51526
• Delvai, M., Steininger, A. (2006). Asynchronous Logic Design - from Concepts to Implementation. In The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications - Volume 1 (pp. 81–86). Peer-reviewed.
  HDL: 20.500.12708/51528
• Delvai, M., Steininger, A. (2006). A Practical Comparison of Logic Design Styles. In The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications - Volume 3 (pp. 61–66). Peer-reviewed.
  HDL: 20.500.12708/51530
• Tummeltshammer, P., Steininger, A. (2006). Time-Multiplexed Multiple Constant Multiplication. In Junior Scientist Conference 2006 (pp. 77–78). Peer-reviewed.
  HDL: 20.500.12708/51570
• Stratil, H., Schmid, U. (2006). Efficient Position-based Communication in Wireless Ad-hoc Networks. In Junior Scientist Conference 2006 (pp. 75–76). Peer-reviewed.
  HDL: 20.500.12708/51571
• Handl, T., Steininger, A. (2006). Implementation of an FPGA-Based Hardware Fault Injector. In Junior Scientist Conference 2006 (pp. 23–24). Peer-reviewed.
  HDL: 20.500.12708/51572
• Albeseder, D., Widder, J. (2006). Simulating Distributed Real-Time Systems. In Junior Scientist Conference 2006 (pp. 83–84). Peer-reviewed.
  HDL: 20.500.12708/51573
• El Salloum, C., Steininger, A., Tummeltshammer, P. (2006). Recovery Mechanisms for Dual Core Architectures. In 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006, Proceedings (pp. 380–388). Peer-reviewed.
  HDL: 20.500.12708/51601
• Proske, M., Trödhandl, C. (2006). Anytime, Everywhere - Approaches to Distance Labs in Embedded Systems Education - Extended Abstract. In Proceedings of ICTTA 2006 (pp. 205–206). IEEE. Peer-reviewed.
  HDL: 20.500.12708/51633
• Proske, M., Trödhandl, C., Handl, T. (2006). Distance Labs - Embedded Systems @home. In Journal of Computational Information Systems (pp. 435–444). Peer-reviewed.
  HDL: 20.500.12708/51634 / Project: SCDL
• Hutle, M., Malkhi, D., Schmid, U., Zhou, L. (2006). Brief Announcement: Chasing the Weakest System Model for Implementing Omega and Consensus. In Stabilization, Safety, and Security of Distributed Systems. 8th International Symposium on Stabilization, Safety, and Security of Distributed Systems, Dallas, Non-EU. Peer-reviewed.
  HDL: 20.500.12708/51635
• Trödhandl, C., Weiss, B., Handl, T., Proske, M. (2006). Environments for Remote Teaching in Embedded Systems Courses. In 2006 ERCIM / DECOS Workshop on Dependable Embedded Systems. ERCIM / DECOS Workshop on Dependable Embedded Systems, Cavtat, Non-EU. Peer-reviewed.
  HDL: 20.500.12708/51656 / Project: SCDL
• Moser, H., Schmid, U. (2006). Optimal clock synchronization revisited: Upper and lower bounds in real-time systems. In Principles of Distributed Systems (pp. 94–109). Peer-reviewed.
  HDL: 20.500.12708/51661
• Moser, H., Schmid, U. (2006). Construction of a Fault-Tolerant Wireless Communication Topology Using Distributed Agreement. In Junior Scientiest Conferenve 2006 (pp. 47–48). Peer-reviewed.
  HDL: 20.500.12708/51662
• Moser, H., Thallner, B. (2006). Construction of a Fault-Tolerant Wireless Communication Topology Using Distributed Agreement. In DIWANS ’06: Proceedings of the 2006 workshop on Dependability issues in wireless ad hoc networks and sensor networks (pp. 35–43). Peer-reviewed.
  HDL: 20.500.12708/51663
• Moser, H., Thallner, B. (2006). Reconciling Distributed Computing Models and Real-Time Systems. In Proceedings of the 27th IEEE Real-Time Systems Symposium (RTSS’06) (pp. 73–76). Peer-reviewed.
  HDL: 20.500.12708/51664

2005

• Kopetz, H., Obermaisser, R., Schmid, U. (2005). Dependable Embedded Systems Research at TU Vienna. Elektrotechnik Und Informationstechnik : E i, 122(1), 33–37. Invited and peer-reviewed.
  DOI: 10.1007/BF03054020
• Albeseder, D., Függer, M., Breitenecker, F., Löscher, T., Tauböck, S. M. (2005). Small PC-Network Simulation -- A Comprehensive Performance Case Study. Simulation News Europe, 44/45, 26–32.
  HDL: 20.500.12708/173433
• Schmid, U., Kopetz, H., Puschner, P., Mayerhofer, L., Steininger, A., Grünbacher, H., Kastner, W., Krall, A. (2005). Antrag UNI-Infrastruktur III, Embedded Systems Research Cluster.
  HDL: 20.500.12708/33035
• Schöberl, M. (2005). Design and Implementation of an Efficient Stack Machine. In Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International (IPDPS) (p. 159). Peer-reviewed.
  HDL: 20.500.12708/51004
• Armengaud, E., Steininger, A., Horauer, M. (2005). Efficient Stimulus Genereation for Remote Testing of Distributed Systems - The Flexray Example. In Proceedings of the 10th IEEE Internationla Conference on Emerging Technologies and Factory Automation (pp. 763–770). IEEE. Peer-reviewed.
  HDL: 20.500.12708/51082 / Project: STEACS
• Hutle, M., Widder, J. (2005). Self-Stabilizing Failure Detector Algorithms. In IASTED International Conference on Parallel and Distributed Computing and Networks (pp. 485–490). Peer-reviewed.
  HDL: 20.500.12708/51119
• Hutle, M., Widder, J. (2005). On the Possibility and the Impossibility of Message-Driven Self-Stabilizing Failure Detection. In Self Stabilizing Systems (pp. 153–170). Peer-reviewed.
  HDL: 20.500.12708/51122
• Widder, J., Le Lann, G., Schmid, U. (2005). Failure Detection with Booting in Partially Synchronous Systems. In Dependable Computing Conference - EDCC5 (pp. 20–37). Peer-reviewed.
  HDL: 20.500.12708/51123
• Hutle, M., Widder, J. (2005). Brief Announcement: On the Possibility and the Impossibility of Message-Driven Self-Stabilizing Failure Detection. In Proceedings of the 24th ACM Symposium on Principles of Distributed Computing (p. 208). Peer-reviewed.
  HDL: 20.500.12708/51124
• Biely, M., Le Lann, G., Schmid, U. (2005). Proof-Based System Engineering Using a Virtual System Model. In Service Availability (pp. 164–179). Peer-reviewed.
  HDL: 20.500.12708/51125
• Thallner, B., Moser, H. (2005). Topology Control for Fault-Tolerant Communication in Highly Dynamic Wireless Networks. In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (pp. 89–100). Peer-reviewed.
  HDL: 20.500.12708/51126
• Weiss, B., Gridling, G., Proske, M. (2005). A Case Study in Efficient Microcontroller Education. In Proceedings Workshop on Embedded Systems Education WESE 2005 (pp. 36–43). Peer-reviewed.
  HDL: 20.500.12708/51127
• Stratil, H. (2005). Distributed Construction of an Underlay in Wireless Networks. In Proceedings of the Second European Workshop on Wireless Sensor Networks (pp. 176–187). Peer-reviewed.
  HDL: 20.500.12708/51128
• Stratil, H. (2005). Fault Tolerant Topology Control with unreliable Failure Detectors. In Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems (pp. 767–772). Peer-reviewed.
  HDL: 20.500.12708/51130
• Stratil, H. (2005). Voronoi supported communication in Wireless ad-hoc Networks. In The 2nd International Symposium on Voronoi Diagrams in Science and Engineering (pp. 105–116). Peer-reviewed.
  HDL: 20.500.12708/51131
• Albeseder, D. (2005). Evaluation of Message Delay Correlation in Distributed Systems. In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (pp. 139–150). Peer-reviewed.
  HDL: 20.500.12708/51132
• Kottke, T., Steininger, A. (2005). Designoptimierung eines Prozessors mit Eigenfehlererkennung. In 16. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen; (pp. 55–59). Peer-reviewed.
  HDL: 20.500.12708/51133
• Delvai, M., Fuchs, G., Handl, T., Huber, W., Steininger, A. (2005). Design of an Asynchronous Microprocessor with Four-State Logic. In Austrochip 2005 (pp. 105–112). Peer-reviewed.
  HDL: 20.500.12708/51134
• Armengaud, E., Rothensteiner, F., Steininger, A., Pallierer, R., Horauer, M., Zauner, M. (2005). A Structured Approach for the Systematic Test of Embedded Automotive Communication Systems. In Proceedings International Test Conference 2005 (pp. 21–28). IEEE Computer Society. Peer-reviewed.
  HDL: 20.500.12708/51142 / Project: STEACS
• Pallierer, R., Horauer, M., Zauner, M., Steininger, A., Armengaud, E., Rothensteiner, F. (2005). A Generic Tool for Systematic Tests in Embedded Automotive Communication Systems. In Embedded World 2005. unbekannt.
  HDL: 20.500.12708/51143 / Project: STEACS
• Armengaud, E., Steininger, A., Horauer, M. (2005). An Efficient Test and Diagnosis Environment for Communication Controllers. In Austrochip 2005. Austrochip, Graz, Austria, Austria. ??? Peer-reviewed.
  HDL: 20.500.12708/51144 / Project: STEACS
• Le Lann, G., Schmid, U. (2005). Proof-Based Systems Engineering in ASSERT. In Proof-Based Systems Engineering in ASSERT. Data Systems in Aerospace, Edinburgh, EU.
  HDL: 20.500.12708/51168
• Fetzer, C., Süßkraut, M., Schmid, U. (2005). On the Possibility of Consensus in Asynchronous Systems with Finite Average Response Times. In On the Possibility of Consensus in Asynchronous Systems with Finite Average Response Times (pp. 271–280). IEEE Computer Society. Peer-reviewed.
  HDL: 20.500.12708/51169
• Legourski, V., Trödhandl, C., Weiss, B. (2005). A System for Automatic Testing of Embedded Software in Undergraduate Study Exercises. In Proceedings Workshop on Embedded Systems Education (WESE’05) (pp. 44–51). Peer-reviewed.
  HDL: 20.500.12708/51170
• Armengaud, E., Rothensteiner, F., Steininger, A., Horauer, M. (2005). A Flexible Hardware Architecture for Fast Access on Large Non-Volatile Memories. In Proceedings of IEEE Workshop on Design Diagnostics of Electronic Circuits Systems (DDECS) 2005 (pp. 113–120). Peer-reviewed.
  HDL: 20.500.12708/51172 / Project: STEACS
• Armengaud, E., Steininger, A., Horauer, M. (2005). A Method for Bit Level Test and Diagnosis of Communication Services. In Proceedings of IEEE Workshop on Design Diagnostics of Electronic Circuits Systems (DDECS) 2005 (pp. 69–74). Peer-reviewed.
  HDL: 20.500.12708/51174 / Project: STEACS
• Hermant, J.-F., Widder, J. (2005). Implementing Reliable Distributed Real Time Systems with the Theta Model. In 9th International Conference on Principles of Distributed Systems (pp. 259–271). Peer-reviewed.
  HDL: 20.500.12708/51175

2004

• Weiss, B., Gridling, G. (2004). Creating and Grading Multiple-Choice Exams.
  HDL: 20.500.12708/32943
• Schmid, U., Weiss, B. (2004). Synchronous Byzantine Agreement under Hybrid Process and Link Failures.
  HDL: 20.500.12708/32974
• Schmid, U. (2004). Failure Model Coverage under Transient Link Failures.
  HDL: 20.500.12708/32975
• Rahbaran, B. (2004). Die Wichtigsten Kommandos in der dc_shell(synopsys).
  HDL: 20.500.12708/32976
• Schmid, U., Weiss, B. (2004). Fault-Tolerant Distributed Algorithms in Sparse Ad Hoc Wireless Networks.
  HDL: 20.500.12708/32977
• Stratil, H. (2004). Design of a Voronoi-Aided Routing (VAR) Protocol for Wireless Sensor Networks.
  HDL: 20.500.12708/32978
• Fuchs, G., Schmid, U., Steininger, A. (2004). Ein Verfahren für das verteilte Generieren eines fehlertoleranten adaptiven Taktes in Hardware.
  HDL: 20.500.12708/32979 / Project: DARTS
• Schmid, U. (2004). Final Report START-Project Y41.
  HDL: 20.500.12708/32980
• Hermant, J.-F., Widder, J. (2004). Implementing Time Free Designs for Distributed Real-Time Systems (A Case Study).
  HDL: 20.500.12708/32981
• Hutle, M., Widder, J. (2004). Time Free Self-Stabilizing Local Failure Detection.
  HDL: 20.500.12708/32982
• Hutle, M., Widder, J. (2004). On the Possibility and the Impossibility of Time Free Self-Stabilizing Failure Detection.
  HDL: 20.500.12708/32983
• Thallner, B. (2004). Distributed Construction of Fault-Tolerant Overlay Networks: Propose Modules.
  HDL: 20.500.12708/32984
• Moser, H., Thallner, B. (2004). Distributed Construction of Fault-Tolerant Overlay Networks: Construction Algorithm.
  HDL: 20.500.12708/32985
• Rahbaran, B. (2004). Performing Automatic Physical Injection of Signal-Flips and Delay Faults with the toolset FIDYCO.
  HDL: 20.500.12708/32986
• Stratil, H. (2004). The usage of the Delaunay Triangulation (resp. the Voronoi Diagram) in dynamic wireless ad-hoc networks.
  HDL: 20.500.12708/32987
• Schmid, U., Steininger, A. (2004). Dezentrale Fehlertolerante Taktgenerierung in VLSI Chips.
  HDL: 20.500.12708/32988
• Steininger, A., Handl, T., Fuchs, G. (2004). EPOCAL - Exploring the Potential of Code Alternation Logic.
  HDL: 20.500.12708/32989
• Fuchs, G., Schmid, U., Steininger, A. (2004). DARTS - Distributed Algorithms for Robust Tick Synchronization.
  HDL: 20.500.12708/32990
• Steininger, A., Delvai, M., Huber, W. (2004). Code Alternation Logic -- A Novel and Efficient Method for Delay-Insensitive Asynchronous Circuits.
  HDL: 20.500.12708/32991
• Huber, W., Steininger, A., Delvai, M. (2004). Delay Insensitive Asychronous Pipeline Implementation for Code Alternation Logic.
  HDL: 20.500.12708/32992
• Steininger, A., Delvai, M., Huber, W. (2004). Synchronous and Asynchronous Design Methods -- A Hardware Designer’s Perspective.
  HDL: 20.500.12708/32993
• Steininger, A., Delvai, M., Huber, W. (2004). Code Alternation Logic (CAL): A Novel Efficient Design Approach for Delay-Insensitive Asynchronous Circuits.
  HDL: 20.500.12708/32994
• Delvai, M., Steininger, A., Huber, W. (2004). Solving the Fundamental Problem of Digital Design -- A Systematic Review of Design Methods.
  HDL: 20.500.12708/32995
• Armengaud, E., Steininger, A., Horauer, M. (2004). Monitoring and Replay hardware -- Requirements and Concepts.
  HDL: 20.500.12708/32996 / Project: STEACS
• Armengaud, E., Horauer, M. (2004). Monitoring and Replay Hardware -- Specification and Implementation.
  HDL: 20.500.12708/32997 / Project: STEACS
• Armengaud, E., Steininger, A. (2004). Automatic Parameter Detection for Communication Protocols.
  HDL: 20.500.12708/32998 / Project: STEACS
• Armengaud, E. (2004). FlexRay Parameter Classification.
  HDL: 20.500.12708/32999 / Project: STEACS
• Armengaud, E. (2004). Accurate Diagnosis Method with Access to Bit-Level.
  HDL: 20.500.12708/33000 / Project: STEACS
• Armengaud, E., Steininger, A. (2004). Fault Injection Method.
  HDL: 20.500.12708/33001 / Project: STEACS
• Armengaud, E., Steininger, A., Horauer, M. (2004). Fault Injection -- Requirements and Concepts.
  HDL: 20.500.12708/33002 / Project: STEACS
• Armengaud, E., Rothensteiner, F., Steininger, A., Horauer, M. (2004). A Flexible Hardware Architecture for Fast Access on Large Non-Volatile Memories.
  HDL: 20.500.12708/33003 / Project: STEACS
• Steininger, A., Horauer, M., Armengaud, E. (2004). Options for Remote Diagnosis in Automotive Distributed Networks.
  HDL: 20.500.12708/33004 / Project: STEACS
• Rahbaran, B., Steininger, A. (2004). A Strategy for Experimental Fault Injection into an Asynchronous Processor.
  HDL: 20.500.12708/33005
• Kottke, T., Steininger, A. (2004). A Reconfigurable Generic Dual Core Architecture.
  HDL: 20.500.12708/33006
• El Salloum, C., Steininger, A. (2004). Recovery Mechanisms for Dual Core Architectures.
  HDL: 20.500.12708/33007
• Tummeltshammer, P., Pueschel, M., Steininger, A., Überhuber, C. W. (2004). Constant Multiplication Methods.
  HDL: 20.500.12708/33008
• Tummeltshammer, P., Pueschel, M., Steininger, A., Überhuber, C. W. (2004). Face Recognition on ASICs.
  HDL: 20.500.12708/33009
• Fetzer, C., Schmid, U. (2004). On the Possibility of Consensus in Asynchronous Systems with Finite Average Response Times.
  HDL: 20.500.12708/33010
• Thallner, B., Schmid, U. (2004). Distributed Construction of Sparse Fault-Tolerant Overlay Networks.
  HDL: 20.500.12708/33011
• Stratil, H. (2004). An efficient implementation of the greedy forwarding strategy.
  HDL: 20.500.12708/33012
• Horauer, M., Rothensteiner, F., Zauner, M., Armengaud, E., Steininger, A., Friedl, H., Pallierer, R. (2004). An FPGA based SoC Design for Testing Embedded Automotive Communication Systems employing the FlexRay Protocol. In Austrochip 2004 (pp. 119–123). TU-Wien. Peer-reviewed.
  HDL: 20.500.12708/50973 / Project: STEACS

2003

• Thaller, K., Steininger, A. (2003). A Transparent Online Memory Test for Simultaneous Detection of Functional Faults and Soft Errors in Memories. IEEE Transactions on Reliability, 52(4), 413–422. Peer-reviewed.
  HDL: 20.500.12708/174824
• Scherrer, C., Steininger, A. (2003). Dealing With Dormant Faults in an Embedded Fault-Tolerant Computer System. IEEE Transactions on Reliability, 52(4), 512–522. Peer-reviewed.
  HDL: 20.500.12708/174825
• Delvai, M., Eisenmann, U., Elmenreich, W. (2003). A Generic Architecture for Integrated Smart Transducers. Lecture Notes in Computer Science, 2778, 733–744.
  HDL: 20.500.12708/174844
• Vilanek, J., Schmid, U., Kastner, W., Weiss, B., Puschner, P., Elmenreich, W., Deinhart, H., Meyer, W. (2003). Projektbericht Technische Informatik: Seamless Campus.
  HDL: 20.500.12708/32898
• Huber, W., Handl, T. (2003). Simulation von Signalen selbstdefinierten Typs in verschiedenen Stufen des Design-Flows.
  HDL: 20.500.12708/32899
• Biely, M. (2003). Towards an optimal algorithm for hybrid Byzantine agreement.
  HDL: 20.500.12708/32904
• Le Lann, G., Schmid, U. (2003). How to maximize computing systems coverage.
  HDL: 20.500.12708/32905
• Le Lann, G., Schmid, U. (2003). How to implement a timer-free perfect failure detector in partially synchronous systems.
  HDL: 20.500.12708/32906
• Schmid, U., Weiss, B. (2003). Impossibility results and lower bounds for consensus under link failures.
  HDL: 20.500.12708/32908
• Thallner, B., Schmid, U. (2003). Fault tolerant communication topologies for wireless ad hoc networks.
  HDL: 20.500.12708/32909
• Widder, J., Le Lann, G., Schmid, U. (2003). Perfect failure detection with booting in partially synchronous systems.
  HDL: 20.500.12708/32910
• Widder, J., Schmid, U. (2003). Booting clock synchronization in partially synchronous systems with hybrid node and link failures.
  HDL: 20.500.12708/32911

2002

• Vilanek, J. (2002). Zutrittskontrolle und Überwachung der Laborräume des Instituts für Technische Informatik.
  HDL: 20.500.12708/32800
• Delvai, M. (2002). Handbuch für SPEAR (Scalable Processor for Embedded Applications in Real-Time Environments).
  HDL: 20.500.12708/32848
• Huber, W. (2002). Peripherieanbindung an SPEAR Extension Modules.
  HDL: 20.500.12708/32849
• Schmid, U., Fetzer, C. (2002). Randomized asynchronous consensus with imperfect communications.
  HDL: 20.500.12708/32907

2001

• Schmid, U., Schossmaier, K. (2001). How to reconcile fault-tolerant interval intersection with the Lipschitz condition. Distributed Computing, 14(2), 101–111. Peer-reviewed.
  HDL: 20.500.12708/174811
• Schmid, U. (2001). Applied Research: A Scientist’s Perspective. Annual Reviews in Control, 25, 183–190. Peer-reviewed.
  HDL: 20.500.12708/174812
• Biely, M., Schmid, U. (2001). Message-efficient consensus in presence of hybrid node and link faults.
  HDL: 20.500.12708/32915
• Weiss, B., Schmid, U. (2001). Consensus with written messages under link faults. In Proc. 20th Symposium on Reliable Distributed Systems (SRDS’01) (pp. 194–197). Peer-reviewed.
  HDL: 20.500.12708/50920
• Schmid, U., Eickhoff, M., Richter, Ch., Krötz, G., Schmitt-Landsiedel, D. (2001). Etching Characteristics and Mechanical Properties of a-SiC:H Thin Films. SENSORS AND ACTUATORS A-PHYSICAL, 94(1–2), 87–94. Peer-reviewed.
  DOI: 10.1016/s0924-4247(01)00691-4

2000

• Schmid, U. (2000). Orthogonal accuracy clock synchronization. Chicago Journal of Theoretical Computer Science, 3, 3–77.
  HDL: 20.500.12708/174813
• Schmid, U., Kastner, W., Burgstaller, B., Kral, C. (2000). Skriptum zur Laborübung “Prozeßautomatisierung.”
  HDL: 20.500.12708/32876
• Kastner, W., Weiss, B., Schmid, U. (2000). Beispielsammlung zur Laborübung Prozeßautomatisierung (TR 183/1-106-b).
  HDL: 20.500.12708/32879
• Schmid, U., Horauer, M., Kerö, N. (2000). How to distribute GPS-time over COTS-based LANs. In Proc. of the 31st IEEE Precise Time and Time Interval Systems and Application Meeting (PTTI’99) (pp. 545–560). Peer-reviewed.
  HDL: 20.500.12708/50921
• Schmid, U. (2000). Applied Research: A Scientist’s Perspective. In Proc. of the joint 25th IFAC/IFIP Workshop on Real-Time Programming (WRTP’00) and Workshop on Algorithms and Architectures for Real-Time Control (AARTC’00) (pp. 5–12).
  HDL: 20.500.12708/50922
• Horauer, M., Kerö, N., Schmid, U. (2000). A network interface for highly accurate clock synchronization. In Proc. AUSTROCHIP’00 (pp. 93–101).
  HDL: 20.500.12708/50923
• Schmid, U. (2000). High-Accuracy Time Services and Fault-Tolerant Clock Synchronization. In Workshop on “Time and Dependability” (pp. 39–57).
  HDL: 20.500.12708/50924

1999

• Weiss, B., Gridling, G., Schmid, U., Schossmaier, K. (1999). The SimUTC fault-tolerant distributed systems simulation toolkit. In Proc. 7th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOT’99) (pp. 68–75).
  HDL: 20.500.12708/50925
• Schmid, U., Nachtnebel, H. (1999). Experimental evaluation of high-accuracy time distribution in a COTS-based Ethernet LAN. In Proc. 24th IFAC/IFIP Workshop on Real-Time Programming (WRTP’99) (pp. 59–68). Peer-reviewed.
  HDL: 20.500.12708/50926
• Schmid, U., Weiss, B., Gridling, G., Schossmaier, K. (1999). A unified approach for simulation and experimental evaluation of fault-tolerant distributed systems. In Proc. of the IASTED International Conference on Applied Modelling and Simulation (AMS’99) (pp. 43–48).
  HDL: 20.500.12708/50927

1998

• Schmid, U. (1998). Internet-Based Real-Time Computing. In Proc. 22nd Annual International Computer Software Applications Conference (COMPSAC’98) (pp. 338–342).
  HDL: 20.500.12708/50928
• Horauer, M., Schmid, U., Schossmaier, K. (1998). NTI: A Network Time Interface M-Module for High-Accuracy Clock Synchronization. In Proc. 6th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS’98) (pp. 1067–1076). Peer-reviewed.
  HDL: 20.500.12708/50930
• Nachtnebel, H., Kerö, N., Cadek, G., Mandl, T., Schmid, U. (1998). Rapid Prototyping mit programmierbarer Logik anhand eines Fallbeispiels. In Tagungsband der TMÖ-Fachtagung Austrochip´98 (pp. 99–104).
  HDL: 20.500.12708/68313

1997

• Schossmaier, K., Schmid, U., Horauer, M., Loy, D. (1997). Specification and Implementation of the Universal Time Coordinated Synchronization Unit (UTCSU). Real-Time Systems, 12(3), 51–84. Peer-reviewed.
  DOI: 10.1023/A:1007953214631
• Schossmaier, K., Schmid, U., Horauer, M., Loy, D. (1997). Specification and Implementation of the Universal Time Coordinated Synchronization Unit (UTCSU). Real-Time Systems, 12, 295–327. Peer-reviewed.
  HDL: 20.500.12708/174324
• Schmid, U., Schossmaier, K. (1997). Interval-Based Clock Synchronization. Real-Time Systems, 12(2), 173–228. Peer-reviewed.
  HDL: 20.500.12708/174814
• Horauer, M., Schmid, U., Schossmaier, K. (1997). NTI: A Network Time Interface M-Module for High-Accuracy Clock Synchronization.
  HDL: 20.500.12708/30997
• Höchtl, D., Schmid, U. (1997). Long-Term Evaluation of GPS Timing Receiver Failures. In Proc. of the 29th IEEE PTTI Systems and Application Meeting (PTTI’97) (pp. 165–180). Peer-reviewed.
  HDL: 20.500.12708/50929

1996

• Schmid, U., Kastner, W. (1996). DOBOS: A Distributed Object-Based Operating System for Soft Real-Time Systems. In Echtzeitsysteme und objektorientierter Entwurf (pp. 3–13). Vieweg-Verlag.
  HDL: 20.500.12708/25331
• Horauer, M., Loy, D., Schmid, U. (1996). NTI Functional and Architectural Specification.
  HDL: 20.500.12708/30996

1995

• Schmid, U., Blieberger, J. (1995). On non-preemptive LCFS Scheduling with Deadlines. Journal of Algorithms, 18(1), 124–158.
  DOI: 10.1006/jagm.1995.1004
• Schmid, U. (1995). Synchronized Universal Time Coordinated for Distributed Real-Time Systems. Control Engineering Practice, 3(6), 877–884. Peer-reviewed.
  HDL: 20.500.12708/174815
• Schmid, U., Pusterhofer, A. (1995). SSCMP: The Sequenced Synchronized Clock Message Protocol. Computer Networks and ISDN Systems, 27, 1615–1632.
  HDL: 20.500.12708/174816
• Schmid, U. (1995). Random Trees in Queueing Systems with Deadlines. Theoretical Computer Science, 144(1–2), 277–314. Peer-reviewed.
  HDL: 20.500.12708/174817
• Schmid, U., Loy, D., Kastner, W. (1995). Project proposal SSCMP: Sequenced Synchronized Clock Multicast Protocol.
  HDL: 20.500.12708/32892
• Schmid, U., Kastner, W., Haberstroh, H. (1995). Process Control Education for Computer Science: From Fiction Back to Facts. In Proceedings TEMPUS JEP 07759 MODIFY Workshop on Automation and Control Engineering in Higher Education (pp. 135–147).
  HDL: 20.500.12708/50919
• Halang, W. A., Koller, F.-J., Schmid, U., Witte, M. (1995). Untersuchung des Zeitverhaltens Verteilter Echtzeitsysteme. In Proc. Echtzeit’95 (pp. 101–107).
  HDL: 20.500.12708/50931

1994

• Schmid, U. (1994). Monitoring Distributed Real-Time Systems. Real-Time Systems, 7, 33–56. Peer-reviewed.
  HDL: 20.500.12708/174818
• Schmid, U., Kastner, W. (1994). DOBOS: Ein Distributed Object-based Operating System für Soft Real-Time Systems. In Proceedings Echtzeit’94 (pp. 130–137).
  HDL: 20.500.12708/50918
• Schmid, U. (1994). Synchronized UTC for Distributed Real-Time Systems. In Proc. IFAC Workshop on Real-Time Programming (WRTP’94) (pp. 101–107). Peer-reviewed.
  HDL: 20.500.12708/50932
• Schmid, U. (1994). Monitoring of Distributed Real-Time Systems. In Proc. NATO ASI on Real-Time Computing (pp. 582–583).
  HDL: 20.500.12708/50933
• Schmid, U. (1994). The Role of Standards in Real-Time Computing. In Proc. NATO ASI on Real-Time Computing (pp. 638–639).
  HDL: 20.500.12708/50934

1993

• Drmota, M., Schmid, U. (1993). The Analysis of the Expected Successful Operation Time of Slotted ALOHA. IEEE Transactions on Information Theory, 39(5), 1567–1577. Peer-reviewed.
  DOI: 10.1109/18.259641
• Schmid, U., Kastner, W. (1993). DOBOS - Konzept eines distributed object-based operating systems.
  HDL: 20.500.12708/32891
• Schmid, U., Haberstroh, H., Stöckler, S. (1993). Process Control Education for Computer Science: Facts and Fiction. In Proceedings SEFI/TEMPUS JEP 2011 - IMPACT Workshop on Computer Science Topics for Control Engineering Education (pp. 13–22).
  HDL: 20.500.12708/50944

1992

• Blieberger, J., Schmid, U. (1992). FCFS Scheduling in a Hard Real-Time Environment under Rush-Hour Conditions. BIT Numerical Mathematics, 32(3), 370–383. Peer-reviewed.
  DOI: 10.1007/bf02074875
• Schmid, U., Blieberger, J. (1992). Some Investigations on FCFS Scheduling in Hard Real-Time Applications. Journal of Computer and System Sciences, 45(3), 493–512. Peer-reviewed.
  DOI: 10.1016/0022-0000(92)90036-i
• Blieberger, J., Schmid, U. (1992). Preemptive LCFS Scheduling in Hard Real-Time Applications. Performance Evaluation, 15(3), 203–215. Peer-reviewed.
  DOI: 10.1016/0166-5316(92)90035-f
• Schmid, U. (1992). On a Tree Collision Resolution Algorithm in Presence of Capture. RAIRO Informatique Theorique et Applications / Theoretical Informatics and Applications, 26(2), 163–197.
  HDL: 20.500.12708/174820
• Schmid, U. (1992). The Average CRI-Length of a Tree Collision Resolution Algorithm in Presence of Multiplicity-Dependent Capture Effects. In Proceedings 19th International Colloquium on Automata, Languages, and Programming (ICALP’92) (pp. 223–234). Springer-Verlag, LNCS. Peer-reviewed.
  HDL: 20.500.12708/50935

1991

• Blieberger, J., Schmid, U. (1991). Qualifying Dynamic Task Scheduling in Hard Real-Time Systems: A Novel Approach.
  HDL: 20.500.12708/32871

2025

• Müller-Gritschneder, D., Lieber, P. (2025, August 16). Combining TinyML Model-based Architecture Methods for Predictive Maintenance in Highly Regulated Environments [Presentation]. AI Solution Days 2025, Nürnberg, Germany.
  HDL: 20.500.12708/219807
• Müller-Gritschneder, D. (2025, June 25). Towards an Automated Toolchain and Fusion-based Instruction Identification for RISC-V Custom Extensions [Conference Presentation]. 2nd Austrian RISC-V Meetup, Graz, Austria.
  HDL: 20.500.12708/220428
• Müller-Gritschneder, D. (2025, May 30). Low Overhead Fault Tolerance for tinyML and Security Applications [Presentation]. 3rd Workshop on Intelligent Methods for Test and Reliability, Tallinn, Estonia. Invited.
  HDL: 20.500.12708/219806

2024

• Bammer, F., Huemer, F. F. (2024, November 26). 2D Inline R2R-Measurement with a Polarization Camera [Conference Presentation]. 23rd international Coating Symposium, Dormagen, Germany.
  HDL: 20.500.12708/209024
• Bammer, F., Huemer, F. F. (2024, September 19). Flächige Schichtdickenerfassung in Echtzeit mit bildgebender Ellipsometrie [Conference Presentation]. Netzwerk ZfP 2024, Linz, Austria.
  HDL: 20.500.12708/209025
• Müller-Gritschneder, D. (2024, September 11). Rapid Prototyping Methods for custom-tailored, safe and secure RISC-V processors [Conference Presentation]. TRISTAN Technical Conference 2024, Graz, Austria.
  HDL: 20.500.12708/206261
• Mueller-Gritschneder, D., Geier, J. (2024, September). Open Source Simulators for Pre-Silicon Validation of Safety-critical RISC-V System-on-chip [Conference Presentation]. Open Source Summit 2024, Wien, Austria.
  HDL: 20.500.12708/206489
• Kuznets, R. (2024, April 9). Reasoning about Knowledge in Byzantine Distributed Systems [Presentation]. Computational Logic Seminar, United States of America (the). Invited.
  HDL: 20.500.12708/200368 / Project: ByzDEL
• Bammer, F., Huemer, F. F. (2024, March 6). Inline Thickness Measurement with a Polarization Camera [Conference Presentation]. LOPEC 2024, Munich, Germany.
  HDL: 20.500.12708/209432
• Kuznets, R. (2024, January 17). What Proof Theory Can Do for You [Presentation]. Seminar on Applied Mathematical Logic 2024, Prague, Czechia.
  HDL: 20.500.12708/193705 / Project: ByzDEL

2023

• van Ditmarsch, H., Kuznets, R., Randrianomentsoa, R. F. (2023, October 6). Simplicial Introduction [Presentation]. Prague CELIA Workshop 2023, Prague, Czechia.
  HDL: 20.500.12708/192758 / Project: ByzDEL
• Girlando, M., Kuznets, R., Marin, S., Morales, M., Straßburger, L. (2023, September 27). Intuitionistic S4 and its decidability [Conference Presentation]. Mosaic Workshop 2023, Wien, Austria.
  HDL: 20.500.12708/192652 / Project: ByzDEL
• Kuznets, R. (2023, February 24). Messages Agents Send; Agents Who Send Messages [Keynote Presentation]. DFG-GACR Research Project CELIA: First Project Meeting 2023, Bayreuth, Germany. Invited.
  HDL: 20.500.12708/192722 / Project: ByzDEL
• Kuznets, R. (2023, January 28). On Interpolation [Conference Presentation]. Fitting at 80, New York, NY, United States of America (the). Invited.
  HDL: 20.500.12708/192762 / Project: ByzDEL

2022

• van der Giessen, I., Jalali, R., Kuznets, R. (2022, November 1). Nested Sequents, Kripke Models, and Uniform Interpolation [Conference Presentation]. Proof-theoretic and algebraic aspects of (intuitionistic) modal logics, Utrecht, Netherlands (the). Invited.
  HDL: 20.500.12708/135862 / Project: ByzDEL
• Randrianomentsoa, R. F., Rincon Galeana, H., Schmid, U. (2022, October 24). Towards a Topological Semantics for Epistemic Reasoning in Byzantine Fault-Tolerant Distributed Systems [Conference Presentation]. Workshop on Connections between Epistemic Logic and Topology (CELT’22), University of Amsterdam, Netherlands (the).
  HDL: 20.500.12708/153197 / Project: ByzDEL
• van Ditmarsch, H., Fruzsa, K., Kuznets, R. (2022, September 6). Framing faultiness Kripke style [Conference Presentation]. MOSAIC: Modalities in Substructural Logics: Theory, Methods and Applications, Kick Off Conference, Capaccio Paestum, Italy.
  HDL: 20.500.12708/153663 / Download: PDF / Project: ByzDEL
• Prabakaran, B. S. (2022, July). Hardware and Software Architectures for Energy-Efficient Smart Healthcare Systems [Poster Presentation]. 2022 Design Automation Conference, United States of America (the).
  HDL: 20.500.12708/152496
• Cignarale, G. (2022, January 18). A Tribute to Philosophical A Priori Knowledge Research in the Design and Analysis of Fault-Tolerant Distributed Systems [Conference Presentation]. Meeting Eight Ticamore, Wien, Austria.
  HDL: 20.500.12708/153250 / Project: ByzDEL

2021

• Fruzsa, K., Kuznets, R., Schmid, U. (2021, November 2). Knowledge-based analysis of the Firing Rebels problem [Presentation]. Research Seminar Informatica 2021, Heerlen, Netherlands (the). Invited.
  HDL: 20.500.12708/193728 / Project: ByzDEL
• Tauner, S., Telesklav, M., Halder, L. (2021). Hardware-Assisted Control Flow Integrity Schemes on RISC-V. Second International Workshop on Secure RISC-V (SECRISC-V), Virtual, Unknown. Invited.
  HDL: 20.500.12708/87276
• Kuznets, R., Marin, S., Strassburger, L. (2021). Intuiting Duals of Proofs. Milano Logic Group Logic Lunch Seminar Series, online, Italy, Italy. Invited.
  HDL: 20.500.12708/87263 / Project: ByzDEL
• Schmid, U. (2021). Honors at TU Wien. International Conference on Talent Development and Honors Education (World of Talent 2021), Groningen, The Netherlands, Netherlands (the). Invited.
  HDL: 20.500.12708/87249

2020

• Kuznets, R., Lellmann, B. (2020). Interpolation for Intermediate Logics via Injective Nested Sequents. Online Partout Seminar, online, France, France. Invited.
  HDL: 20.500.12708/87072 / Project: ByzDEL

2019

• Kuznets, R., Prosperi, L., Schmid, U., Fruzsa, K. (2019). Byzantine Causal Cone. Workshop on Formal Reasoning in Distributed Algorithms (FRiDA), Wien, Austria. Invited.
  HDL: 20.500.12708/86905
• Kuznets, R. (2019). Extrapolating Interpolation. Proof Theory in Logic workshop, Utrecht, Netherlands (the). Invited.
  HDL: 20.500.12708/86880
• Kuznets, R. (2019). Causality in the Age of Fake News. Seminar “Logic and Theoretical Computer Science”, University of Bern (2019), Bern, Switzerland. Invited.
  HDL: 20.500.12708/86904
• Paulweber, P., Maier, J., Cortadella, J. (2019). Unified (A)Synchronous Circuit Development. 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2019), Hirosaki, Japan.
  HDL: 20.500.12708/86909
• Schmid, U. (2019). Digital Modeling of Asynchronous Integrated Circuits. 2nd Workshop on Hardware Design and Theory (https://sites.google.com/view/motimedina/hdt-2019, colocated with DISC 2019), Budapest, Hungary.
  HDL: 20.500.12708/86974
• Kuznets, R. (2019). Time and Retrocausality in Distributed Systems. Goedel’s Legacy, Wien, Austria.
  HDL: 20.500.12708/86975
• Kuznets, R., Lellmann, B. (2019). Translating Quantitative Semantic Bounds into Nested Sequents. Fifth TICAMORE MEETING, Wien, Austria. Invited.
  HDL: 20.500.12708/86976

2018

• Kuznets, R. (2018). Interpolation using sequents and their generalisations. PhDs in Logic X, Prag, Czechia. Invited.
  HDL: 20.500.12708/86799
• Gréaux, L., Kuznets, R., Prosperi, L., Schmid, U. (2018). What do Byzantine agents know? First joint workshop by the Mathematics and the Philosophy Research Institutes of UNAM, Mexiko-Stadt, Mexico. Invited.
  HDL: 20.500.12708/86037

2017

• Shafique, M. (2017). Approximate Computing across the Hardware and Software Stacks. Invited Talks at TU Eindhoven, Eindhoven, Netherlands (the). Invited.
  HDL: 20.500.12708/86684
• Shafique, M. (2017). Cross-Layer Approximate Computing: From Circuits to Applications. Invited Talks at University of Twente, Twente, Netherlands (the). Invited.
  HDL: 20.500.12708/86683
• Shafique, M. (2017). Low-Power Computing and Emerging Trends. CPS Summer School 2017, Porto Contr Ricerche, Italy.
  HDL: 20.500.12708/86679
• Shafique, M. (2017). Enabling Extreme Energy-Efficiency through Brain-Inspired Computing Trends: From Approximate to Neural Processing. 15th International Conference On Frontiers of Information Technology (FIT’17), Islamabad, Pakistan. Invited.
  HDL: 20.500.12708/86678
• Shafique, M. (2017). Emerging Brain-Inspired Computing Trends: From Approximate Computing to Neural Processing. International Conference On Latest Trends in Electrical Engineering and Computing Technologies (INTELLECT’17), Karachi, Pakistan. Invited.
  HDL: 20.500.12708/86677
• Shafique, M. (2017). Robust Heterogeneous Computing for CPS. CPS Summer School 2017, Porto Contr Ricerche, Italy.
  HDL: 20.500.12708/86575
• Kuznets, R. (2017). The Byzantine Mind. Seminar Logic and Theoretical Computer Science, University of Bern (2017), Bern, Switzerland. Invited.
  HDL: 20.500.12708/86565

2016

• Konnov, I., Lazić, M., Veith, H., Widder, J. (2016). Parameterized Verification of Liveness of Distributed Algorithms. Workshop on Formal Reasoning in Distributed Algorithms (FRiDA), Wien, Austria.
  HDL: 20.500.12708/86425
• Lazić, M., Konnov, I., Veith, H., Widder, J. (2016). Model Checking of Threshold-based Fault-Tolerant Distributed Algorithms. 7th Workshop on Program Semantics, Specification and Verification: Theory and Applications, St. Petersburg, Russian Federation (the). Invited.
  HDL: 20.500.12708/86426
• Zeiner, M., Schwarz, M., Winkler, K., Schmid, U. (2016). Broadcasting in Random Trees. ALEA in Europe - Young Researchers Workshop, TU Wien, Austria.
  HDL: 20.500.12708/86332
• Schmid, U. (2016). Easy Impossibility Proofs for k-Set Agreement. Dagstuhl Seminar #16282 Topological Methods in Distributed Computing, Wadern, Germany. Invited.
  DOI: 10.4230/DagRep.6.7.31
• Schmid, U. (2016). Reconciling Fault-Tolerance and Robustness ? Workshop on Design and Analysis of Robust Systems @ CPS-Week 2016, Hofburg Vienna, Austria, Austria. Invited.
  HDL: 20.500.12708/86399

2015

• Zeiner, M., Függer, M., Nowak, T., Schmid, U. (2015). Optimal Strategies for Repeated Leader Election. Joint Austrian-Hungarian Mathematical Conference 2015, Györ, Hungary.
  HDL: 20.500.12708/86086

2013

• Hofbauer, M., Schweiger, K., Gaberl, W., Zimmermann, H., Giesen, U., Langner, F., Schmid, U., Steininger, A. (2013). Single Event Transient Pulse Shape Measurements by On-chip Sense Amplifiers in a Single Inverter for Intermediate Input States under Alpha Particle Irradiation. IEEE Nuclear and Space Radiation Effects Conference (NSREC), San Francisco, United States of America (the).
  HDL: 20.500.12708/85741
• Zeiner, M., Függer, M., Schmid, U., Kößler, A., Nowak, T. (2013). The Effect of Forgetting on the Performance of a Synchronizer. 18th ÖMG Congress and Annual DMV Meeting, Universität Innsbruck, Austria.
  HDL: 20.500.12708/85720
• Dolev, D., Függer, M., Hofstätter, M., Lenzen, C., Perner, M., Posch, M., Schmid, U., Sigl, M., Steininger, A. (2013). FATAL+HEX: Fault-Tolerant Self-Stabilizing Clock Generation+Distribution. Poster Session at the CSAIL Industry Affiliates Program (CSAIL-IAP) Annual Meeting, Cambridge, United States of America (the).
  HDL: 20.500.12708/85710

2012

• Dolev, D., Függer, M., Lenzen, C., Schmid, U. (2012). Towards Self-stabilizing Byzantine Fault-Tolerant Clock Generation in Systems-on-Chip. NITRD Workshop, Baltimore, United States of America (the). Invited.
  HDL: 20.500.12708/85536
• John, A., Konnov, I., Schmid, U., Veith, H., Widder, J. (2012). Who is afraid of Model Checking Distributed Algorithms? PUMA/RISE Seminar, Traunkirchen, Austria.
  HDL: 20.500.12708/85435
• John, A., Konnov, I., Schmid, U., Veith, H., Widder, J. (2012). Parameterized Model Checking of Fault-tolerant Distributed Algorithms. Dagstuhl Seminar 12461: Games and Decisions for Rigorous Systems Engineering, Dagstuhl, Germany. Invited.
  HDL: 20.500.12708/85432
• John, A., Konnov, I., Schmid, U., Veith, H., Widder, J. (2012). Counter Attack against Byzantine Generals. Alpine Verification Meeting, IST Austria, Austria.
  HDL: 20.500.12708/85359
• Konnov, I., Veith, H., Widder, J. (2012). Who is afraid of Model Checking Distributed Algorithms? Workshop on Exploiting Concurrency Efficiently and Correctly, Berkeley, United States of America (the).
  HDL: 20.500.12708/85358
• Hofbauer, M., Schweiger, K., Dietrich, H., Zimmermann, H., Voss, K. O., Merk, B., Schmid, U., Steininger, A. (2012). Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating through a 90 nm Bulk CMOS Inverter Chain. Nuclear and Space Radiation Effects Conference (NSREC), Miami, United States of America (the).
  HDL: 20.500.12708/89963

2011

• Függer, M., Widder, J. (2011). On Efficient Checking of Link-reversal-based Concurrent Systems. PUMA/RISE Seminar, Traunkirchen, Austria.
  HDL: 20.500.12708/85311

2010

• Függer, M. (2010). Fault-Tolerant Distribiuted on-chip Algorithms. RiSE GUGGING (IST AUSTRIA), Gugging (IST Austria), Austria. Invited.
  HDL: 20.500.12708/85069
• Függer, M. (2010). Fault-Tolerant Distribiuted on-chip Algorithms. PUMA 2010, Szentendre, Hungary, EU. Invited.
  HDL: 20.500.12708/85071
• Kößler, A. (2010). Challenges in Fault-Tolerant Distribiuted Real-Time Systems. RiSE Workshop TU Graz, Szentendre, Hungary, EU.
  HDL: 20.500.12708/85072
• Függer, M. (2010). Fault-Tolerant Distribiuted on-chip Algorithms. FK 2010 (Forschungskooperation TU Wien - UNI Brno), Brno, Czech Republic, EU. Invited.
  HDL: 20.500.12708/85070

2007

• Jahn, P., Polzer, T. (2007). Graphical Microcontroller Programming (GMCP). IEEE International Conference on Industrial Informatics - INDIN 2007, Wien, Austria.
  HDL: 20.500.12708/84609

2006

• Widder, J., Gridling, G., Weiss, B., Blanquart, J.-P. (2006). Synchronous Consensus with Mortal Byzantines. Dagstuhl Seminar 06371. From Security to Dependability, Dagstuhl, EU. Invited.
  HDL: 20.500.12708/84588
• Schmid, U. (2006). Wissenschaftliche Forschung - Quo vadis? IKT in Österreich 2006, Wien, Austria. Invited.
  HDL: 20.500.12708/84587
• Steininger, A. (2006). The DARTS project. ESA Workshop, Aarhus, Denmark.
  HDL: 20.500.12708/84591
• Steininger, A. (2006). The ECS group’s hardware related research activities. Firma Freescale, München, EU.
  HDL: 20.500.12708/84590

2005

• Delvai, M., Steininger, A. (2005). ASPEAR - An Asynchronous 16 Bit RISC Processor Core. Siemens PSE Technology Day, Vienna, Austria, Austria.
  HDL: 20.500.12708/84458

2004

• Widder, J. (2004). Why, Where and How to Use the Theta-Model. Seminaire Reflecs in INRIA Rocquencourt, Frankreich, INRIA Rocquencourt, Frankreich, Austria. Invited.
  HDL: 20.500.12708/84388
• Widder, J. (2004). VLSI Design and the Theta-Model (Kurzvorstellungen aktueller Forschung). Diskussionskreis Fehlertoleranz, Berlin, Austria.
  HDL: 20.500.12708/84387
• Schmid, U. (2004). The Theta-Model. Diskussionskreis Fehlertoleranz, Berlin, Austria.
  HDL: 20.500.12708/84386
• Widder, J. (2004). The Theta-Model, and how to Boot Clock Synchronization in it. Seminaire Reflecs in INRIA Rocquencourt, Frankreich, INRIA Rocquencourt, Frankreich, Austria. Invited.
  HDL: 20.500.12708/84385

2003

• Delvai, M., Eisenmann, U., Elmenreich, W. (2003). A Generic Architecture for Integrated Smart Transducers. International Conference, FPL 2003, Lissabon, Portugal, Austria. Peer-reviewed.
  HDL: 20.500.12708/84208

2001

• Schmid, U. (2001). Versuch über die wahre Art, das Clavier zu spielen. Berufungsvortrag, Vienna, Austria, Austria.
  HDL: 20.500.12708/84189

1997

• Schmid, U. (1997). Challenges in Interval-based Clock Synchronization. Dagstuhl-Seminar 9728 on “Average Case Analysis of Algorithms,” Schloß Dagstuhl, Germany, Austria. Invited.
  HDL: 20.500.12708/84187

1995

• Schmid, U. (1995). “Echtzeit”-Systeme. Habilitationskolloquium, Wien, Austria.
  HDL: 20.500.12708/84194

1993

• Schmid, U. (1993). On Random-Trees Arising in the Analysis of Scheduling Algorithms for Real-Time Systems. Dagstuhl-Seminar 9328 on “Average Case Analysis of Algorithms,” Schloß Dagstuhl, Germany, Austria. Invited.
  HDL: 20.500.12708/84196

2024

• Müllner, M. (2024). Modeling resource utilization for spiking neural networks in FPGAs [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2024.94824 / Download: PDF
• Spitzer, J. (2024). Implementation of an automated fault-injection framework for QDI circuits [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2024.107665 / Download: PDF
• Salzmann, J. (2024). Waveform Prediction of Digital Circuits by Sigmoidal Approximation [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2024.96722 / Download: PDF
• Tabassam, Z. (2024). Utilizing and extending the inherent fault tolerance properties of asynchronous QDI circuits [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2024.122341 / Download: PDF
• Fruzsa, K. (2024). Agents’ knowledge and Its limits in byzantine fault-tolerant distributed systems [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2024.124621 / Download: PDF
• Baumann, D. (2024). Simulating chemical reactions with a well-founded lattice Boltzmann approach [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2024.120609 / Download: PDF
• Haschke, O. (2024). Comparison of QDI adders [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2024.107664 / Download: PDF
• Kukovec, J. (2024). SMT-driven techniques for verifying distributed systems [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2025.128661 / Download: PDF
• Ferdowsi, A. (2024). Modeling of digital delays in multi-input gates and applications [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2025.131184 / Download: PDF

2023

• Wiedemann, S. M. (2023). go2async: a high-level synthesis tool for asynchronous circuits based on click-elements [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2023.97424 / Download: PDF
• Pacheiner, P. (2023). Comprehensive characterization of consensus solvability in dynamic networks with transient stability [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2023.86340 / Download: PDF
• Tran, T. H. (2023). Symbolic verification of TLA+ specifications with applications to distributed algorithms [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2024.117518 / Download: PDF

2022

• Dür, W. (2022). Fault-tolerant GALS architecture based on pausable clocking [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2022.88760 / Download: PDF
• Pircher, C. (2022). Smart SoC testing and remote configuration facilitated by the use of IJTAG complemented with on-chip microprocessor access [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2022.98141 / Download: PDF
• Öhlinger, D. (2022). Beta-CIDM: A faithful and composable delay model with adversarial noise [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2022.87144 / Download: PDF
• Schwendinger, M. (2022). Evaluation of different tools for design and fault-injection of asynchronous circuits [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2022.98624 / Download: PDF

2021

• Telesklav, M. (2021). Implementations, improvements implications of hardware-assisted CFG-based control flow integrity schemes [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2021.72945 / Download: PDF
• Stoilkovska, I. (2021). Modeling and verification of synchronous fault-tolerant distributed algorithms [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2021.90331 / Download: PDF
• Behal, P. (2021). Quantitative Comparison of the sensitivity of delay-insensitive design templates to transient faults [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2021.81601 / Download: PDF
• Echtinger-Sieghart, C. (2021). IoT implementation and evaluation of distributed consensus algorithms [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2021.85743 / Download: PDF
• Felber, S. (2021). On the strongest message adversary for directed dynamic networks [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2022.87145 / Download: PDF
• Maier, J. (2021). Proper abstractions for digital electronic circuits: A physically guided approach [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2022.102506 / Download: PDF

2020

• Schaumberger, N. (2020). Automatic competitive analysis of real-time scheduling algorithms for firm-deadline tasks with non-preemptible sections and precedence constraints [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2020.70863 / Download: PDF
• Schlögl, T. (2020). An Extension framework for epistemic reasoning in Byzantine distributed systems [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2020.69444 / Download: PDF

2019

• Lazić, M. (2019). Reduction techniques for parameterized model checking and synthesis of fault-tolerant distributed algorithms [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2019.67803 / Download: PDF
• Ramsl, W. (2019). Fault masking in synchronous and in asynchronous logic - a comparsion [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2019.25573 / Download: PDF
• Perner, M. (2019). Fault-tolerant clock distribution in grid-like networks [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2019.72064 / Download: PDF

2018

• Pfleger, D. (2018). Knowledge and communication complexity in distributed systems [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2018.40116 / Download: PDF
• Fritz, B. (2018). Operation and verification framework for the FRad experimental ASIC [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2018.23746 / Download: PDF
• Schwarz, M. (2018). Agreement algorithms in directed dynamic networks [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2018.57089 / Download: PDF
• Obermüller, J. (2018). SoC FPGA Oszilloskop : Implementierung eines Oszilloskops auf einem FPGA mit eingebettetem Prozessor [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/80024

2017

• Schütz, M. (2017). COTS FPGAs in space : From old concerns to new possibilities [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2017.54551 / Download: PDF
• Huemer, F. F. (2017). Protecting 4-phase delay-insensitive communication against transient faults [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2017.30269 / Download: PDF
• Fimml, P. (2017). Temporal-epistemic logic in Byzantine message-passing contexts [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2017.38943 / Download: PDF
• Savulimedu Veeravalli, V. (2017). Design of custom ASIC for radiation experiments to study single event effects [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2017.48221 / Download: PDF

2016

• Hermann, C. (2016). ASCARTS - design of an asynchronous processor using a high-level specification language [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2016.21820 / Download: PDF

2015

• Gmeiner, A. (2015). Parameterized model checking of fault-tolerant distributed algorithms [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2015.33793 / Download: PDF

2014

• Lechner, J. (2014). Building robust GALS circuits : fault-tolerant and variation-aware design. Techniques for reliable circuit operation [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2014.25096 / Download: PDF
• Resch, S. (2014). Composability for fail-safe safety-critical systems [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2014.27500 / Download: PDF
• Heinisch, A. (2014). Selection and hardware-implementation of an efficient consensus algorithm for a mesochronous system [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2014.22245 / Download: PDF
• Trenkwalder, C. (2014). Effekte von Stuck-At Faults in Delay-Insensitiver Logik [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2014.26284 / Download: PDF
• Kößler, A. (2014). Real-time performance analysis of synchronous distributed systems [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2014.22342 / Download: PDF
• Kutschera, R. (2014). Efficient interfacing between timing domains [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2014.25542 / Download: PDF
• Maier, J. (2014). Online test vector insertion - a concurrent built-in self-testing (CBIST) approach for asynchronous logic [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2014.25295 / Download: PDF

2013

• Hofbauer, F. (2013). Analoge Q-Control zur Güteverstärkung von piezoelektrischen MEMS Resonatoren [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/159679
• Hagmann, A. (2013). Performance aware hardware runtime monitors [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/159732
• Pados, K. D. (2013). Design and evaluation of an AXI4 bus system [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/159734
• Perner, M. (2013). Self-stabilizing Byzantine fault-tolerant clock distribution in grids [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2013.21901 / Download: PDF
• Schwarz, M. (2013). Solving k-Set agreement in dynamic networks [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2013.21843 / Download: PDF
• Naqvi, S. R. (2013). A non-blocking fault-tolerant asynchronous networks-on-chip router [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2013.22599 / Download: PDF
• Hechinger, O. (2013). Analysis of the failure behavior of memory management units [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2013.23180 / Download: PDF
• Winkler, K. (2013). Easy impossibility proofs for k-set agreement [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2013.22720 / Download: PDF
• Polzer, T. (2013). A digital metastability model for VLSI circuits [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2013.22620 / Download: PDF
• Hofstätter, M. (2013). Solving the labeling problem : a Byzantine fault-tolerant self-stabilizing FPGA prototype based on the FATAL+ protocol [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2013.21760 / Download: PDF

2012

• Panhofer, T. (2012). Self-healing asynchronous circuits for high-reliability applications [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-47033
  HDL: 20.500.12708/11331 / Download: PDF
• Fuchs, B. (2012). Elaboration of a Fault-tolerance strategy for space-borne digital signal processing applications [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-46481
  HDL: 20.500.12708/11402 / Download: PDF
• Ferringer, M. (2012). Asynchronous logic in real-time systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-46960
  HDL: 20.500.12708/11411 / Download: PDF
• Pavlovic, M. (2012). Implementation of a distributed computation framework [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/159720
• Posch, M. (2012). Selbststabilisierende byzantinisch fehlertolerante Takterzeugung in FPGAs [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/160584

2011

• Resch, S. (2011). Hardware description with timing requirements [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-48081
  HDL: 20.500.12708/10654 / Download: PDF
• Birner, M. (2011). SPEAR2C : implementation of a cache controller for SPEAR2 [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-59473
  HDL: 20.500.12708/10682 / Download: PDF
• Friesenbichler, W. (2011). Effects and mitigation of transient faults in quasi delay-insensitive logic [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-48162
  HDL: 20.500.12708/11332 / Download: PDF
• Najvirt, R. (2011). Description methods for asynchronous circuits : a comparison [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-41766
  HDL: 20.500.12708/12697 / Download: PDF
• Walter, M. (2011). The SPEAR2 Hardware/Software Interface [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/159954
• Burker, A. (2011). Implementation of the TTP/A protocol and WCET analysis on the SPEAR2 platform [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/160444

2010

• Robinson, P. (2010). Weak system models for fault-tolerant distributed agreement problems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-42017
  HDL: 20.500.12708/12220 / Download: PDF
• Nowak, T. (2010). Topology in Distributed Computing [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-30814
  HDL: 20.500.12708/13126 / Download: PDF
• Függer, M. (2010). Analysis of on-chip fault-tolerant distributed algorithms [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-39917
  HDL: 20.500.12708/14747 / Download: PDF
• Hofer, M. (2010). Generic microprocessor-controlled test unit [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/159779

2009

• Polzer, T. (2009). Fault-tolerant hardware implementation of a consensus algorithm [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-37200
  HDL: 20.500.12708/12587 / Download: PDF
• Fuchs, G. (2009). Fault-tolerant distributed algorithms for on-chip tick generation: concepts, implementations and evaluations [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-33442
  HDL: 20.500.12708/13033 / Download: PDF
• Widtmann, C. (2009). High-level system modeling with SystemC and TLM [Master Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-25914
  HDL: 20.500.12708/14675 / Download: PDF
• Moser, H. (2009). A model for distributed computing in real-time systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-29073
  HDL: 20.500.12708/8949 / Download: PDF
• Ambrosch, K. (2009). Mapping stereo matching algorithms to hardware [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-29639
  HDL: 20.500.12708/8962
• Biely, M. (2009). Dynamic aspects of modelling distributed computations [Dissertation, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/184232
• Jahn, P. (2009). Automated regression testing of embedded devices [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/186055
• Tummeltshammer, P. (2009). Analysis of common cause faults in dual core architectures [Dissertation, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/186533

2008

• Klein, W. (2008). Self-oscillation as a time-reference in asynchronous logic - the UART example [Master Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-20396
  HDL: 20.500.12708/10909 / Download: PDF
• Mosser, J. (2008). AMBA4SPEAR2: an AMBA extension module for the SPEAR2 processor core [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-27846
  HDL: 20.500.12708/11047 / Download: PDF
• Armengaud, E. (2008). A transparent online test approach for time-triggered communication protocols [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-23226
  HDL: 20.500.12708/11092 / Download: PDF
• Fletzer, M. (2008). SPEAR2 - an improved version of SPEAR [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-19088
  HDL: 20.500.12708/11836 / Download: PDF
• Lechner, J. (2008). Implementation of a design tool for generation of FSL circuits [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/182090
• Jeitler, M. (2008). Optimization of FSL gates [Master Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/183557

2007

• Walter, C. (2007). Simulation and performance evaluation of a topology control algorithm in NS2 [Master Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-14919
  HDL: 20.500.12708/13959 / Download: PDF
• Prokop, H. (2007). Reconfigurable hardware implementation of polynomial arithmetic over the finite field GF(3) [Master Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/178009

2006

• Stratil, H. (2006). Advantages and limitations of position-based communication in wireless ad-hoc networks [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-14382
  HDL: 20.500.12708/10175 / Download: PDF
• Függer, M. (2006). Fault-tolerant distributed clock generation in VLSI systems-on-chip [Master Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-28679
  HDL: 20.500.12708/10193 / Download: PDF
• Varga, C. (2006). Analyse der Implementierbarkeit einer aktiven Schallunterdrückungslösung in Hardware [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-32417
  HDL: 20.500.12708/12081 / Download: PDF
• Ferringer, M. (2006). An asynchronous hardware design for distributed tick generation [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/179556
• Krupnik, L. (2006). Oszillatorische Blutdruckmessung für Patienten mit Rotationsblutpumpen [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/186913

2005

• Hutle, M. (2005). Failure detection in sparse networks [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-21522
  HDL: 20.500.12708/12762 / Download: PDF
• Huber, W. (2005). Design of an asynchronous processor based on code alternation logic - exploration of delay insensitivity [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-18234
  HDL: 20.500.12708/13907 / Download: PDF
• Moser, H. (2005). Distributed construction of a fault-tolerant wireless communication topology for networked embedded systems oder “Implementing the Thallner-algorithm” [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-12392
  HDL: 20.500.12708/9602 / Download: PDF
• Schöberl, M. (2005). JOP: a Java optimized processor for embedded real-time systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-9003
  HDL: 20.500.12708/9614 / Download: PDF
• Rahbaran, B. (2005). An experimental comparison of robustness between synchronous and asynchronous logic design [Dissertation, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/177677
• Kottke, T. (2005). Untersuchung von fehlertoleranten Prozessorarchitekturen für sicherheitsrelevante Automobilanwendungen [Dissertation, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/177711
• Thallner, B. (2005). Topology control for fault-tolerant communication in wireless ad hoc networks [Dissertation, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/180401
• Gallo, R. (2005). Revision and verification of an enhanced UART [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/180580

2004

• Widder, J. (2004). Distributed computing in the presence of bounded asynchrony [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-13246
  HDL: 20.500.12708/14277 / Download: PDF
• Delvai, M. (2004). Design of an asynchronous processor based on code alternation logic - treatment of non-linear data paths [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-13195
  HDL: 20.500.12708/9609 / Download: PDF
• Albeseder, D. (2004). Experimentelle Verifikation von Synchronitätsannahmen für Computernetzwerke [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/181067
• Handl, T. (2004). Implementierung eines FPGA-basierten Hardware-Fehlerinjektors [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/184082
• Tummeltshammer, P. (2004). Multiple constant multiplication by time-multiplexed mapping of addition chains [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/184119

2003

• Fuchs, G. (2003). A superscalar 16 bit microcontroller for real-time applications [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-11271
  HDL: 20.500.12708/12155 / Download: PDF
• Rieder, B. (2003). Xerxes error behavior [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-10803
  HDL: 20.500.12708/8680 / Download: PDF
• Pedram, T. (2003). Asynchrone Realisierung einer Arithmetic Logic Unit [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/183013
• Winkler, M. (2003). Integrating time-triggered distributed system design in MATLAB/Simulink [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/183455
• Eggenhofer, M. (2003). Entwicklung eines USB fullspeed VHDL-Cores [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/183637
• El Salloum, C. (2003). Realisierung eines generischen Online Debuggers für Embedded Systems [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/185821

2002

• Biely, M. (2002). Byzantine agreement under the perception-based fault model [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-77933
  HDL: 20.500.12708/13521 / Download: PDF
• Widder, J. (2002). Switching on : how processes initialize for consistent broadcast [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-77756
  HDL: 20.500.12708/13550 / Download: PDF
• Weiss, B. (2002). Authenticated consensus [Dissertation, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/179189
• Rahimi Movaghar, S. (2002). Comparison of protocol frameworks [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/181787
• Eisenmann, U. (2002). Design and implementation of a highly efficient communication node for real-time applications [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/185224
• Jankela, M. (2002). Realization of a re-usable offline debugger for the SPEAR micro-controller [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/185819
• Resanka, C. (2002). Communication protocol test device in VHDL [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/186234
• Stratil, H. (2002). Topology management and routing in wireless networks : an overview [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/186446

2001

• Vilanek, J. (2001). Zur Rolle der Verifikation im Designprozess digitaler integrierter Schaltungen [Dissertation, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/179306
• Thaller, K. (2001). A transparent online memory test [Dissertation, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/180075

• Daniel Müller-Gritschneder: Best Paper Award: Moritz Thoma, Tobias Preintner, Emad Aghajanzadeh, Shambhavi Balamuthu Sampath, Pierpaolo Mori, Nael Fasfous, Manoj-Rohit Vemparala, Alexander Frickenstein, Daniel Mueller-Gritschneder, Ulf Schlichtmann; Uncertainty Aware Training to Improve Uncertainty Active Learning for Semantic Segmentation Proceedings of the Computer Vision and Pattern Recognition Conference (CVPR) Workshops, 2025
  2025 / SAIAD Workshop, CVPR25 / USA / Website
• Daniel Müller-Gritschneder: Best Student Paper Award: Pierpaolo Mori, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Moritz Thoma, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Christian Unger, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone "Wino Vidi Vici: Conquering Numerical Instability of 8-Bit Winograd Convolution for Accurate Inference Acceleration on Edge"
  2024 / IEEE/CVF Winter Conference on Applications of Computer Vision 2024 / USA
• Daniel Müller-Gritschneder: Best Paper Award: Samira Ahmadi, Rafael Stahl, Philipp van Kempen, Daniel Mueller-Gritschneder and Ulf Schlichtmann. "Towards Rapid Exploration of Heterogeneous TinyML Systems using Virtual Platforms and TVM’s UMA."
  2023 / Workshop on Compilers, Deployment, and Tooling for Edge AI. / Germany
• Daniel Müller-Gritschneder: Habilitationspreis
  2019 / Bund der Freunde der technischen Universität München / Germany / Website
• Daniel Müller-Gritschneder: Best Paper Award for Paper: Saman Payvar, Mir Khan, Rafael Stahl, Daniel Mueller-Gritschneder, Jani Boutellier "Neural Network-based Vehicle Image Classification for IoT Devices"
  2019 / IEEE International Workshop on Signal Processing Systems, SiPS 2019 / China
• Daniel Müller-Gritschneder: Senior Member
  2019 / IEEE / USA
• Josef Widder: FIT-IT Embedded Systems Dissertationsstipendium "Distributed Computing in the Presence of Bounded Asynchrony"
  2004 / Austria
• Ulrich Schmid: Synchronized Universal Time Coordinated for Distributed Real-Time Systems
  1997 / START-Programm / Austria
• Ulrich Schmid: Kardinal Innitzer Förderungspreis
  1995 / Kardinal-Innitzer-Preis / Austria