Computer Architecture LU


Understanding of pipelined design


Design of a pipelined microprocessor: instruction set design and simulation, pipeline stages, implementation in an FPGA, test and performance evaluation. After comparing existing instruction set architectures (ISAs), students design their own ISA. This ISA is first evaluated in a high-level simulation and then implemented in hardware. The implementation must consider especially the resolution of hazards in a pipelined design. The goal is a processor that runs in an FPGA; its cost and performance are evaluated and compared to other designs.


O.Univ.Prof. Dipl.-Ing. Dr.techn. Herbert GRÜNBACHER

Univ.Ass. Dipl.-Ing. Wolfgang PUFFITSCH



Design your own microprocessor.

There are two basic rules for the design:

  1. The processor has to be pipelined
  2. The processor has to run in an FPGA

Almost everything else is up to you. Be creative!



An introduction talk will be given on October 8, 2010, 9:00, in lecture room EI 2 Pichelmayer. The slides for this talk are available here. Organization details can also be found in the leaflet.


Enrollment is open until October 9, 2010 at myTI. The assignments are to be solved in groups of 4 or 5 (depending on the number of participants); please name your preferred group members upon enrollment.


The lab is in the TI-LAB at Treitlstr. 3, mezzanine, rooms 1 and 2. You can use the lab during the week from 8:00 till 22:00. Each student will get an access card and an account. Please upload your picture on myTI. For questions or issues with regard to the lab access or the lab accounts contact Mr. Deinhart.

Assignments and Dates

The detailed assignments can be found in the lab notes. There are several lab meetings, where the assignments can be submitted and discussed. The dates of these meetings can be found in the leaflet. If there are additional meetings, these will be announced here on the homepage on short notice.


This course supplements the Computer Architecture lecture.

There is also an accompanying Wiki for this course.

Information about the deployed FPGA board can be found here.


For questions regarding this course, please turn to Wolfgang Puffitsch.