The TT-SoC project is supported by FIT-IT, an Austrian research programme initiatiated by the Austrian Federal Ministry of Transport, Innovation, and Technology (BMVIT).

The project is lasting from March 2007 to May 2009.

It is the objective of the TT-SoC research project to lay the foundation for a next-generation embedded system architecture that provides a predictable integrated execution environment for the component-based design of many different types of embedded applications. This project is inspired by the research priorities that have been identified in the ARTEMIS Strategic Research Agenda and is based on the long-standing experience of TU Vienna and TTTech in the field of time-triggered technology in general and on the Integrated Project DECOS funded by the European Union under FP7 in particular. At the core of this project is the design and development of a research prototype of a time-triggered Network on Chip (TT NoC), implemented in an FPGA, for the predictable interconnection of heterogeneous components. A component can be a self-contained computer, including system and application software, an FPGA, or a custom hardware unit. By providing a single standardized interface to all types of components for the exchange of messages, the architecture supports the component-based design of large applications, enables massive reuse of components, and provides the framework for the implementation of fault-handling by reconfiguration and triple-modular redundancy. The TT NoC will offer inherent fault isolation to support the seamless integration of independently developed components, possibly with different criticality levels. Furthermore, mechanisms for integrated resource management will support dynamically changing resource requirements (e.g., different operational modes of an application), fault-tolerance, and a power-aware system behavior.